SKY130 ROM Compiler Project
Вставка
- Опубліковано 8 жов 2024
- I'm introducing a new ROM compiler for the SKY130 Open PDK.
In this episode we mostly introduce the "why" of the project, doing a quick review of the existing options and why a new solution is needed. Then a quick sneak peek into what we'll dive into in the future episodes.
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Links from the video :
tinytapeout.com/
efabless.com/c...
github.com/pol...
openram.org/
Super cools project Looking forward for next episode
Still need to solve the hardest problem: remembering to swap the blank ROM GDS for the one containing your bootloader before tape out
Speaking from experience ? :D
Cool project, I’m looking forward to your upcoming videos on the topic!
Very cool! Excited to see more of this, especially interested in seeing the interface parts of a verilog project that uses the rom!
From the verilog point of view, it'll be seen as a blackbox component / macro that you instantiate explicitly.
I'll probably need to have a simple functional simulation model that can be used for RTL simulation though so you can try out code.
In the future it would be nice of course if the creation of the macro could be automated by yosys directly, but that's further in the future.
Really interesting project! I'm looking forward to seeing more about it, especially if you can go into the details of the toolchain you're using.
Thanks !
Yes, the following video will probably me mostly showing stuff around in Magic ( opencircuitdesign.com/magic/ ) and be much more technical with less of me just talking :)
The tools I used for this project are the fairly common ones used with SKY130: Mostly magic for actual layout design and extraction, xschem for schematic capture, ngspice for simulation, klayout for visualization and also as a secondary DRC check. I've also used FasterCap to do some capacitance estimations/cross-checks.
Then I used gdstk for the actual "compiler". It's just assembling pre-laid out design elements mostly. It's still WIP for some of the more tricky parts.
Hello,
pretty nice layout ! I'm wondering where you found the DRC that includes density? For a chip I sent to manufacturing, I created my own library of logic gates to operate at very low voltage, and I faced a lot of issues with the density, especially the diff/tap. Normally, the foundry adds dummies to fix the problem of density (only if it can find space).
C'est un super beau project en tout cas
Thanks. Density targets are partially listed in the `mpw_precheck` from efabless ( search for 'density' in the git repo ). Some others were recently posted on slack because they changed for the last tape out and caused some issue ( especially poly density where the max was reduced from 60% down to 38% ... ). And yeah, efabless adds fill pattern but the algorithm is not super smart, it just adds the pattern no matter what and it also keeps quite a big clearance around existing features to not disturb anything so if you have a dense design, nothing will be added ...
Very interesting!