Welcome back to Semi Tech channel. This video talks about the short short channel effect namely drain induced barrier lowering and leakage power dissipation due to it.
Hi Edu, If you want to have more audiences for your channel, please create more videos about MOSFET just like this video. Since the background is EE, it is easy to step in semiconductor field such as FINFET. That is one of the ways for you can have more audiences. Wish you the best.
I don't know why they draw higher voltage at lower curve... If this could be calculated somehow it could make it clear. Maybe one of the good explanations found.
source side depletion region cant increase because source is grounded as well as body is grounded too. so here barrier lowering is between source and channel.
Hi Rajneesh, Drain voltage is always more than source voltage but has been represented by a low level curve . Typically drain voltage for short channels are 1.5 -1.8 V
www.semanticscholar.org/paper/Gate-Induced-Drain-Leakage-Current-in-45-nm-CMOS-Yuan-Park/d8ae3db50fdf372b2442a625608be03012c34923 Please refer to the graph to understand current and electron profiles in detail. For energy band diagram and electron profile you can refer to figure 3 of below link www.researchgate.net/figure/Band-diagrams-of-a-gate-substrate-junction-and-b-gate-drain-edge-for-an-nFET_fig3_3140206
Hi Edu, If you want to have more audiences for your channel, please create more videos about MOSFET just like this video. Since the background is EE, it is easy to step in semiconductor field such as FINFET. That is one of the ways for you can have more audiences. Wish you the best.
Sure, we resumed it now. We'll put videos on Finfet soon
your explanation is clear and easy to understand, thank you
much better than other lenghty monotonous videos
thank you
I don't know why they draw higher voltage at lower curve... If this could be calculated somehow it could make it clear.
Maybe one of the good explanations found.
source side depletion region cant increase because source is grounded as well as body is grounded too. so here barrier lowering is between source and channel.
Great 👍👏👏🥰
Very nice explanation! thanks
nice one bro
Nice explanation.
Helpful explanation 🙏
What is drain voltage
Hi Rajneesh,
Drain voltage is always more than source voltage but has been represented by a low level curve . Typically drain voltage for short channels are 1.5 -1.8 V
VERY NICE EXPLANATION
After lot of search here is a nice explanation
Hey what is that electron profile? Can someone explain it?
www.semanticscholar.org/paper/Gate-Induced-Drain-Leakage-Current-in-45-nm-CMOS-Yuan-Park/d8ae3db50fdf372b2442a625608be03012c34923
Please refer to the graph to understand current and electron profiles in detail.
For energy band diagram and electron profile you can refer to figure 3 of below link
www.researchgate.net/figure/Band-diagrams-of-a-gate-substrate-junction-and-b-gate-drain-edge-for-an-nFET_fig3_3140206
Very well explained sir !!
When both the depletion regions met the device will off.am I correct ?
Please correct me if i was wrong
Yes true that
great.
Good explanation
Very well explain sir...
good explanaton
Well explained
Great, thanks
bro please make a video on GIDL ....
Sure , I will put it out soon
Thanks a lot
Most welcome!
YOU HAVE EXPLAINED VERY WELL, EAGER TO SEE MORE VIDEOS. PLEASE MAKE MORE VIDEOS ON ANALOG CIRCUITS AND LAYOUTS
Sure. I will upload for sure
Nice explanation sir. Simple way of explanation for complex things is always good. Keep posting more videos like this
Thank you, I will . Keep watching!