How to design Clock Divided By 4.5 ? Explained!

[@hongsenyu8108]

module f_div_45 (clk, rstn, dout);
input clk, rstn;
output dout;

reg[3:0] count;
reg phase0;
reg phase1;
reg phase1_neg;

//count from 0 to 8
always@(posedge clk, negedge rstn)begin
if(!rstn)
count

[@hongsenyu8108]

Another method with less Flip-Flops by a binary counter that counts from 0 to 8

[@KarthikVippala]

@@hongsenyu8108 Namaste _/\_ , thank you so much for the effort , this will help all of us :)
Good luck & great health .

[@shashwattripathi4129]

Subarashī kontentsu 😁

[@SaikiranReddy-c8p]

Is correct if we approach the problem by using the mod 9 counter and 50 percentage duty cycle we will get it right .....

[@nagamahendrasaiallagadda6186]

Really helpful

[@KarthikVippala]

Namaskaram Mahendra Sai , thanks for the support , good luck & great health :)

[@nagayadav5275]

Hi sir your explanation is very can you make one video for pipeline process in digital electronics it was helpful so great in present

[@KarthikVippala]

Sure I will

[@Rcs9060]

in this videos at 6minutes22sec diagram will come, Q5 output not to connect to OR gate, but in diagram its connected.
in code assign statement, count[5] not there, but in diagram its there

[@Placement_]

module clk_divider(clk_in,clk_out,rstn); // for clk divide by 1.5.
input clk_in,rstn;
output clk_out;
reg [2:0]Q;
reg Q2;
wire clk_out2;
wire clk_out1;
always @(posedge clk_in)
begin
if(rstn)
begin
Q[0]