Lecture 22 HDL verilog: Frequency Divider (Clock Divider) -Shrikanth Shirakol

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  • Опубліковано 23 гру 2024

КОМЕНТАРІ • 32

  • @ramprakash90k
    @ramprakash90k 2 роки тому

    Hi Sir, I think there is a mistake in Calculating the bit number @17:40. Please check the formula once, your formula will give you number of FF's but not the bit number. So here "n" represents number of FF required to achieve 500Hz clk from 1MHz clk. In your example Count[10] will achieve the 500Hz clk output.
    For easy calculation just check deriving 50Hz clk from 100Hz clk with the same formula you mentioned (which is simple divide by 2 ).
    for bit number the formula should be 2^(n+1).
    Apart from that, very good explanation on the freq dividers.
    Waiting for your response. Thank you.

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  2 роки тому +2

      Dear Ram Prakash, your analysis is correct. But how i derived formula is explained in detail in one more video lecture of mine. The link is : ua-cam.com/video/oe42ZY3RNjo/v-deo.html
      Freq division concept starts @ 30:00.
      And thanks for your good words.

    • @ramprakash90k
      @ramprakash90k 2 роки тому +1

      @@shrikanthshirakol3843 Thank you sir for ur quick response. I have gone through the video. It has been corrected in that video.

  • @piyushmaurya9063
    @piyushmaurya9063 3 роки тому

    very informative lecture sir..nicely explained..thankyou

  • @huuthanh6584
    @huuthanh6584 2 роки тому

    Can I see your testbench? Thank you

  • @vlogfreak4411
    @vlogfreak4411 Рік тому

    sir the counter used is synchronous or asynchronous?

  • @shubhamdang2816
    @shubhamdang2816 2 роки тому

    Hello, I have a doubt... ls command is displaying the relative path of the file opened in vim instead of the names of all the contents ... Do you have any idea how to change it to normal Functioning

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  2 роки тому

      Dear Shubham, Can you please elaborate your question? It's bit unclear to me.

  • @rahulpillai3385
    @rahulpillai3385 2 роки тому

    Sir could you provide a test bench for the counter with frequency divider?

  • @fasihahmadjanjua
    @fasihahmadjanjua 2 роки тому

    Sir, How to implement the floating value of n ? (in verilog)
    We round off the value of "n" in these examples, but in several projects we are strictly bound to time constraints So it is necessary to implement floating number for n to precise calculations

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  2 роки тому

      In that case, we use different logic to implement Freq division. Here i have discussed easy one for the beginners.

    • @fasihahmadjanjua
      @fasihahmadjanjua 2 роки тому

      Will you please 🥺 guide me that logic ?

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  2 роки тому

      Will try to make a video lecture on it.

  • @niharachakonda4067
    @niharachakonda4067 2 роки тому

    Pattern detector clock divider anna clock frequency divider anna okatena sir

  • @ShashiKumar-jv2cs
    @ShashiKumar-jv2cs 3 роки тому

    What if we want to divide by a odd number

  • @ravindrababu8989
    @ravindrababu8989 3 роки тому

    how can i generate phase from clock

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  3 роки тому

      Phase of the clock can be varied by forcing the clock after certain delay units. If u can elaborate the need of doing it, i can explain you better

    • @ravindrababu8989
      @ravindrababu8989 3 роки тому

      I want to find frequency & phase by using a clock buffer circuit

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  3 роки тому

      l hope you want to measure clock skew. Phase can be measured by measuring the delay between the two clocks of your focus. Consider 1 period delay to be 360 degree and measure the skew.
      And Freq can be found by taking reciprocal of period.

  • @sarangarasagna4058
    @sarangarasagna4058 4 роки тому

    Sir how to generate a clock of 800 MHz in verilog

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  4 роки тому

      @saranga rasanga, Generation of a clock of 800MHz possible only if the target FPGA kit has the max. Operating frequency more than or equal to 800MHz.
      If you provide me the input frequency, i can help you in getting the required output.

    • @sarangarasagna4058
      @sarangarasagna4058 4 роки тому

      @@shrikanthshirakol3843 sir I want it for writing test bench using timescale

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  4 роки тому

      @@sarangarasagna4058 Clock period, T is reciprocal of Clock frequency f. 1/800MHz = 1.25ns = 1250ps
      time scale to be set is: 1ps/1ps (can be even set in terms of "ns" also)
      Half period of clock = 1250/2= 625ps.
      Testbench for generating clock with 800MHz.
      forever #625 clock= ~ clock;

    • @sarangarasagna4058
      @sarangarasagna4058 4 роки тому +1

      @@shrikanthshirakol3843 sir thank you

    • @mohdanassiddiqui8029
      @mohdanassiddiqui8029 4 роки тому

      Sir how to write test bench code .
      And I want to divide by 10.

  • @jahnavibandaru2337
    @jahnavibandaru2337 3 роки тому

    Sir I want to do 100MHZ clock to 1HZ.please provide the explanation

    • @aravinds4495
      @aravinds4495 3 роки тому +1

      have you completed your task ?

    • @shrikanthshirakol3843
      @shrikanthshirakol3843  2 роки тому

      @jahnavi, please refer to my one more video. The concept starts @30:00. Apply the same formula for the solution to your problem.

  • @bishalghoshb3412
    @bishalghoshb3412 4 роки тому

    Pls sir upload more example video

  • @vegetahead6103
    @vegetahead6103 4 роки тому

    thank you, I learned a lot

  • @stevenpriston4301
    @stevenpriston4301 3 роки тому

    module freq_Div(clk,newclk, newclk1,newclk2,count3);
    input clk;
    output reg newclk =0,newclk1 = 0,newclk2 =0,count3=0 ;
    reg[3:0] count =0,count1=0,count2=0;
    always @(posedge clk)
    begin
    if(count3==1)
    begin
    count =0;
    end
    else
    begin
    count = count + 1;
    newclk = count[0];
    end
    end
    always@(posedge newclk)
    begin
    count1 =count1 +1;
    newclk1 = count1[0];
    end
    always@(posedge newclk1)
    begin
    count2 = count2+1;
    newclk2 = count2[0];
    end
    assign count3 = (count & count2)?1'b1:1'b0;
    endmodule
    im not able to do freqncy divider by 5 rtl code