As per the design the output of the adder should be AB + CD. Since the smallest multiplier is 2bit multiplier( For 1bit we can use AND gate) and the signals here are one bit ,I will use one multiplier instead of two multiplier and one adder. The input of the multiplier will be CB and AD. The oupts of the mulplier will be P0= BD, P1= CD+AB, P2= AC+ Cy1, P3= Cy2. Now I will pass P1 to capture flop and ignore other outputs. Now we have only one multiplier. So delay= 5 + 0.5+ 0.5 = 6ns. Frequency= 166.6 MHz
As per the design the output of the adder should be AB + CD. Since the smallest multiplier is 2bit multiplier( For 1bit we can use AND gate) and the signals here are one bit ,I will use one multiplier instead of two multiplier and one adder. The input of the multiplier will be CB and AD. The oupts of the mulplier will be P0= BD,
P1= CD+AB, P2= AC+ Cy1, P3= Cy2. Now I will pass P1 to capture flop and ignore other outputs.
Now we have only one multiplier. So delay= 5 + 0.5+ 0.5 = 6ns. Frequency= 166.6 MHz
could you please do a vedio on asynchronous fifo