Your pictures and explanation of the structure was good. thanks. i think you have let your personal opinions and bias color the technicals. i wish you had stayed true to explaining the technical differences.
Is "dishing" a problem, or is it intentional? From my understanding, the Cu recess might help to reduce the tensile stress in the SiO₂. By the way, thank you for your informative videos.
Should be intentional. But keep in mind, all ideas are to be verified by HVM. It seems that people know how to do W2W HBI well, but only TSMC can do HBI D2W for now...
thank you for providing the video that is very informative. you presented two equations: y(A)= (1+A*0.223/2)^-2 y(A)= (1+A*1.15/2)^-2 what are the differences in those two equations?
WOW, you caught me. One of them could be misleading. Please check my video about how I came out with the formula (p.14) ua-cam.com/video/tDgG0lO1fS4/v-deo.html
@@王不老說半导 Thank you for your response. I have watched the video and this one as well. ua-cam.com/video/aiP9rL57avQ/v-deo.html It looks like the following equation is for the 0.44X0.44cm die: y(A)= (1+A*1.15/2)^-2 and the following equation is for the 1X1cm die: y(A)= (1+A*0.223/2)^-2 What confuses me is that the x axis of the two graphs is the die size from 0 to 4 square cm. You came up with the two different equations because of different machines used at TSMC, correct? The 0.44X0.44cm die is made in machine A and the 10X10mm die is made in machine B so that you need to use two different yield equations, correct? The yield of the 0.44X0.44cm die at 3.5 square cm is 10%: y(A)= (1+A*1.15/2)^-2 The yield of the 1X1cm die at 3.5 square cm is 52%: y(A)= (1+A*0.223/2)^-2 What does these mean? The two graphs tell me that a larger die size has better yield.
@@王不老說半导 My understanding of the current semiconductor industry's trend is chiplet that avoids larger dies due to the die cost and yield loss. Your presentation has two equations that shows a larger die has better yield that seems against the indusctry's trend.
I also hate those names (does not make any sense and therefore difficult to remember) Check out the story below how Intel name their products. It's not as simple as you think. computerinfobits.com/why-are-intel-processors-named-after-lakes/
best review of packing technologies
Thanks, glad that you like it! best wishes!
thank you sir!! great video!
Thanks!
Your pictures and explanation of the structure was good. thanks. i think you have let your personal opinions and bias color the technicals. i wish you had stayed true to explaining the technical differences.
Good inputs, can you be more specific, e.g., which page and topic?
Great to see your Video, Wei-E!!
Thanks, be well!
ON you slide played around 9:25, there is a typo on the first bullet, instead of 36x33, it should have been 26x33 according to your presentation
You caught me, good eyes!
Is "dishing" a problem, or is it intentional? From my understanding, the Cu recess might help to reduce the tensile stress in the SiO₂.
By the way, thank you for your informative videos.
Should be intentional. But keep in mind, all ideas are to be verified by HVM. It seems that people know how to do W2W HBI well, but only TSMC can do HBI D2W for now...
我老師怎麼看 OSAT 也在發展自己的Advanced package 技術 例如ASE也有自己的2.5D LSI 有機會與foundry 競爭嗎
大家都想自己做，但是都最不好，三星最想做，但是高階的就是做不出來，半導體產業往往有winer takes all的現象，所以其他的要搶搶台積，我很難看好!
I don't know why this guy have so less number suscriber
😂
thank you for providing the video that is very informative.
you presented two equations:
y(A)= (1+A*0.223/2)^-2
y(A)= (1+A*1.15/2)^-2
what are the differences in those two equations?
WOW, you caught me. One of them could be misleading. Please check my video about how I came out with the formula (p.14)
ua-cam.com/video/tDgG0lO1fS4/v-deo.html
@@王不老說半导
Thank you for your response.
I have watched the video and this one as well.
ua-cam.com/video/aiP9rL57avQ/v-deo.html
It looks like the following equation is for the 0.44X0.44cm die: y(A)= (1+A*1.15/2)^-2
and the following equation is for the 1X1cm die: y(A)= (1+A*0.223/2)^-2
What confuses me is that the x axis of the two graphs is the die size from 0 to 4 square cm.
You came up with the two different equations because of different machines used at TSMC, correct?
The 0.44X0.44cm die is made in machine A and the 10X10mm die is made in machine B so that you need to use two different yield equations, correct?
The yield of the 0.44X0.44cm die at 3.5 square cm is 10%: y(A)= (1+A*1.15/2)^-2
The yield of the 1X1cm die at 3.5 square cm is 52%: y(A)= (1+A*0.223/2)^-2
What does these mean?
The two graphs tell me that a larger die size has better yield.
@@mizunommjp exactly, thanks for the reminding. The question is not that critical。 It's the trend that really matters.
@@王不老說半导 My understanding of the current semiconductor industry's trend is chiplet that avoids larger dies due to the die cost and yield loss. Your presentation has two equations that shows a larger die has better yield that seems against the indusctry's trend.
@@mizunommjp The two equations should show trend with smaller yield for larger dies, as those in p.21.
p16 and p17 have a typo. it should not be fervos but foveros.
OOPS, Mybad!
I also hate those names (does not make any sense and therefore difficult to remember)
Check out the story below how Intel name their products. It's not as simple as you think.
computerinfobits.com/why-are-intel-processors-named-after-lakes/