How to design 4 Bit Ripple Carry Counter using Verilog? || S VIJAY MURUGAN || Learn Thought

This video focus on 4 bit ripple carry counter verilog HDL program.
• Verilog HDL PROGRAM | ... - Full Adder Verilog Program
• 4-Bit Ripple Carry Add... - 4Bit Ripple Carry Adder Verilog Program
• Delay Model in Verilog... - Types of delay Model
• Gate Delay in Verilog ... - Gate Delay Model
• Relational, Equality a... - Relational, Equality and bitwise Operator
• Arithmetic & Logical O... - Arithmetic and Logical Operators
• Reduction, Shift, Conc... - Reduction, Shift, Concatenation and Replication Operators
• Design a Verilog Code ... - 2to4 Decoder Verilog Program
• Design of 8:3 Encoder ... - Design 8to3 Encoder using Verilog HDL program
• Comparison of Function... - Difference between Function & Task
• Design of ALU using Ve... - How to design ALU using Verilog HDL Program
• Verilog code for Half ... - Verilog Program for Half Subtractor
• Design of 8:3 Encoder ... - Design 8to3 Encoder using Verilog HDL Program
• Design a Verilog Code ... - Verilog Program for 2 to 4 Decoder
• 4-Bit Ripple Carry Add... - 4 Bit Ripple Carry Adder Verilog HDl Program
• Verilog HDL PROGRAM | ... - Verilog HDl Program for Full Adder Gate Level Modeling
• 4 to 1 MUX Verilog Cod... - Verilog HDL program for 4 to 1 Mux
• Built in Gate Primitiv... - Built in Gate Primitives
• Design of 4 bit Compar... - 4 Bit Comparator verilog HDL Program
• Binary to Gray Code us... - Binary to gray code conversion verilog HDL Program
• How to design 4 Bit Ri... - 4 Bit Ripple Carry Counter Verilog HDL Program
• Realization of D_FF an... - Verilog HDL Code to Realize D-FF
• Verilog HDL Bitwise Op... - Verilog HDL Bitwise Operator
• How to Express Numbers... - How to Express Number System
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[@FluteStream]

Shouldn't the DFF have output q

[@mohamedmezid4821]

// 4-Bit Ripple Carry Counter
module 4B_RCC (clk, reset, q);
input clk, reset;
output [3:0] q;
TFF tff0 (q[0], clk, reset);
TFF tff1 (q[1], q[0], reset);
TFF tff2 (q[2], q[1], reset);
TFF tff3 (q[3], q[2], reset);
endmodule
module TFF (clk, reset, q);
input clk, reset;
output q;
wire d;
DFF dff0 (q, d, clk, reset);
not (d, q);
endmodule
module DFF (q, d, clk, reset);
input d, clk, reset;
output q;
reg q;
always @(posedge reset or negedge clk) begin
if (reset)
q