You can start from any value you like with the help of initial block and it is intialised only once. Here 5 is a random value I have taken. You can choose any value. If your query is still unsolved please let me know.
Verilog videos I have uploaded so far are enough to learn all the verilog concepts. With the help of these knowledge one will be able to write code for a big projects(if tried)
If I have correctly understood your query then you are asking, there must be two end-end before end module. If it's query then it's only one end as we have one begin . If it's not your query then please ask your query again.
Initial is a procedural block and statement inside are executed only once. Here 2 initials are used so that 1) we can initialise the count value only once and 2) execution like counting is not repeated that is once counting criteria is full filled it must stop execution which is not possible with always block.
Both are same logically but not interms of hardware. forever @(posedge clk) means when posedge comes implement the logic forever.so it's a infinite loop. But always is not a loop. We need to understand the concepts in terms of hardware.
1'b0 means 1 bit binary 0 means 0 is a binary digit which is of 1 bit. Like 2'b00 , 3'b011, 4'b1010 so on 3'd7 means 7 is decimal number and it's 3 bit i.e 111 in binary b, d , h are called format specifier for binary,decimal, hexadecimal respectively. Thanks.
Timescale is used for simulation by simulator to define the time.its never used to design a clock signal. It give just timing information and the precision. I will explain about it when I will make a video on writing test cases for memory testing.
Thanks. I have given a code for clock generation with different duty cycle. You can use the same procedure for your query. Watch other videos and I have explained about it
such a great series, Sir ur explanation is excellent and , each point is very clear , too much helpful for us.
Sir how you considered value from 5 initially
You can start from any value you like with the help of initial block and it is intialised only once.
Here 5 is a random value I have taken. You can choose any value.
If your query is still unsolved please let me know.
we can use it in models for example in an clk generation block, one can use forever. There is no hard and fast rule, one has to use it in tb only.
Sir in last example,
count should be = 8'b00000101 because of 8 bit instead of 7'b00000101 ?
You are absolutely right. It's 8 bit.
Thank you so much for pointing out the mistake.
sir , In the counter with diasable block example ig two end statements will come before end module
sir, upto how many videos we have to watch to know about only verilog not about VLSI
Verilog videos I have uploaded so far are enough to learn all the verilog concepts. With the help of these knowledge one will be able to write code for a big projects(if tried)
If I have correctly understood your query then you are asking, there must be two end-end before end module. If it's query then it's only one end as we have one begin . If it's not your query then please ask your query again.
@@ComponentByte i understood but why there two initials are used
Initial is a procedural block and statement inside are executed only once.
Here 2 initials are used so that 1) we can initialise the count value only once and 2) execution like counting is not repeated that is once counting criteria is full filled it must stop execution which is not possible with always block.
Can we get the output only writing code on testbench without writing design codr
No, testbench must instantiate design file to work. It's name is testbench which tests designed hardware. So it must include logic for that hardware.
forever @(posedge clk) what does meaning of this sentence? It is same like always @(posedge clk)
Both are same logically but not interms of hardware.
forever @(posedge clk) means when posedge comes implement the logic forever.so it's a infinite loop.
But always is not a loop. We need to understand the concepts in terms of hardware.
@@ComponentByte Thanks sir!
sir what does ossilate= 1'bo mean..?? 1 stand for here ?? '=?? and bo= mean..??
1'b0 means 1 bit binary 0 means 0 is a binary digit which is of 1 bit.
Like
2'b00 , 3'b011, 4'b1010 so on
3'd7 means 7 is decimal number and it's 3 bit i.e 111 in binary
b, d , h are called format specifier for binary,decimal, hexadecimal respectively.
Thanks.
Sir nice explanation very useful and can you make a video on timescale and an example of 100Mhz clock using timescale
Timescale is used for simulation by simulator to define the time.its never used to design a clock signal. It give just timing information and the precision.
I will explain about it when I will make a video on writing test cases for memory testing.
Nice explanation, please make a video on generation of clock at 25% , 35%,75% ... Duty cycle
Thanks. I have given a code for clock generation with different duty cycle. You can use the same procedure for your query. Watch other videos and I have explained about it