[@bijaysah9135]

Please upload other tutorial. You explain in very detailed way.god bless you

[@chintudewan1437]

Thanks a lot. Please upload complete verilog tutorial.

[@ComponentByte]

Welcome. I will upload all the tutorial one by one.Thanks

[@avromukherjee5463]

Very nice explanation. Thank you for this wonderful video.

[@ComponentByte]

Thank you for your appreciation.

[@andyden8501]

Simple and helpful.Thanks lot.

[@adilbasu7183]

Thanks. Please upload delays with blocking and non blocking assignment

[@ComponentByte]

Very soon I am going to upload blocking and non blocking assignment.

[@sindhujavelayutham5663]

Thanks a lot sir. hope the test bench is same for xilinx also. Is it ?

[@ComponentByte]

Yes. Testbench is same for all the simulator.

[@akashjoshi3186]

sir pls release video on FIFO
i want to learn it and impplement it as my hobby project;

[@ComponentByte]

Noted, I will try. I am not getting time these days to make content. I will try to upload both theory and coding.

[@techfriends5029]

Helpful. Thanks

[@jainammehta6118]

Thanks for sharing

[@ComponentByte]

Most welcome. There are total 5 video tutorial about delay in verilog which covers almost all concepts of delays in verilog. I will upload it soon.Thanks.

[@reshmas3714]

Thank you sir

[@marshalraju6089]

Thanks a lot

[@educationpoint7987]

Good one.thanx

[@akashjoshi3186]

pls do upload FIF0