The 6809e required a quadrature clock input, and I always wondered why. Now I wonder if it had something to do with gating logic between various digital airlocks to avoid race around conditions.
4 phase clocks were common in early CPUs/microprocessors (the TMS9900 from TI required a rather complicated 4 phase non-overlapping clock for example). I suspect Matt is working his way up to D type flip-flops, which are a little more complex, but only change on one type of edge of the clock signal (most commonly the positive edge), which allow designs to be simplified (there can be no race condition as the output only changes to the input state when the clock signal changes in the correct direction. By the time the output has changed the clock edge is over and thus the output feeding back to the input will not have any effect).
Correct, well anticipated. D-types in the next video. I think if there is a big asymmetry between sinking and sourcing current within a gate/circuit then multiphase non-overlapping clocks are basically guaranteed to work in flip-flops etc. Other workarounds for this asymmetry would require a large number of transistors. To extend the analogy, imagine an airlock where you can instantaneously open and close the doors. Then you could be in the airlock and close the door behind and open the one in front at exactly the same time and the air still won't be able to escape the HAB. That's essentially what a D-type does, there isn't enough time for a race around. But if the doors open fast but close slowly, then this won't work. CMOS circuits can easily source and sink large currents (ie. open and close doors fast), but older processes like NMOS, have a big transistor to sink current but a weak pull-up to source current.
For those not in the know, ICs started life using bipolar logic, which was large and power hungry. This was overtaken by PMOS, which needed much less space for a transistor but was slow in comparison (especially going from high to low) and needed multiple power rails. This was replaced by NMOS, which was faster, simpler to design and could use a single power rail. PMOS and NMOS both used a single transistor and a resistor in a pair (NMOS could use a second transistor configured as a resistor, but the idea holds), so one of the two states was always drawing current. CMOS uses a complimentary pair of transistors, one PMOS and one NMOS. When the state changes one transistor turns off and the other on. Current flows only when the state is changing (in theory at least) as the transistors are partially on or off. The 6809 used a pair of clocks, one of which was 50% out of phase with the other (i.e. the second clock changes half way through a 1 or 0 state of the first). To generate this phase difference it needed a crystal that was 4 times the fundamental frequency of the CPU, not a 4 phase clock. The E version of the 6809 used an external clock and you can see the two clocks documented there (E and Q).
I got a couple things to point out. First, your two-relay SR latch actually has the outputs on the outputs of the OR gates/inputs of the inverters, which is the opposite of the logic diagram. (That's fine, though, since it just means the Q and Q-bar outputs end swapped. This matches how they appear on the actual schematic involving relays, so no problems are introduced by this.) This was actually the case in the last couple videos; I just didn't notice it before. It does unfortunately make it hard to represent what's _actually_ happening in your circuit (rather than an approximation) with NOR gates, though. Second, the gated SR latch you actually built has the OFF and common terminals for the SR latch portion swapped compared to the schematic. That's not a problem right now since you aren't using the ON terminals on those relays currently, but there's the possibility it may cause problems for future expansion.
You must have eagle eyes to spot that common and off were swapped, but functionally it doesn't make any difference and i wanted to show the race conditions. Unfortunately, there can be a big gap between filming the circuit and making the video which means sometimes errors like this creep in. For example, I'm currently building/filming and debugging the program counter for the relay6502, but I'm several (5+) videos behind in the production.
@@DrMattRegan I learned in times where was no Internet or not i this form. I learned from book of German autor before I ended primary school. I known about 90% 74 series TTL from memory ;)
Cool, thanks for the feedback! I'm thinking of splitting the series after two more videos. I'll move into semiconductors (7400 series, SRAM, EPROMs etc) in one stream, build the alarm clock, then Turing machine and make it 6502 compatible. This will be the more educational stream. In the other stream, I'm going see if i can take the relays all the way to a relay 6502. I just need to get to the d-type flip-flop and ripple counter in the current series. It will force me to make a more efficient sequencer.
Relay Flip Flop my, favourite genre of music.
Yep, they are strangely mesmerizing.
The 6809e required a quadrature clock input, and I always wondered why. Now I wonder if it had something to do with gating logic between various digital airlocks to avoid race around conditions.
4 phase clocks were common in early CPUs/microprocessors (the TMS9900 from TI required a rather complicated 4 phase non-overlapping clock for example). I suspect Matt is working his way up to D type flip-flops, which are a little more complex, but only change on one type of edge of the clock signal (most commonly the positive edge), which allow designs to be simplified (there can be no race condition as the output only changes to the input state when the clock signal changes in the correct direction. By the time the output has changed the clock edge is over and thus the output feeding back to the input will not have any effect).
Correct, well anticipated. D-types in the next video. I think if there is a big asymmetry between sinking and sourcing current within a gate/circuit then multiphase non-overlapping clocks are basically guaranteed to work in flip-flops etc. Other workarounds for this asymmetry would require a large number of transistors.
To extend the analogy, imagine an airlock where you can instantaneously open and close the doors. Then you could be in the airlock and close the door behind and open the one in front at exactly the same time and the air still won't be able to escape the HAB. That's essentially what a D-type does, there isn't enough time for a race around. But if the doors open fast but close slowly, then this won't work.
CMOS circuits can easily source and sink large currents (ie. open and close doors fast), but older processes like NMOS, have a big transistor to sink current but a weak pull-up to source current.
For those not in the know, ICs started life using bipolar logic, which was large and power hungry. This was overtaken by PMOS, which needed much less space for a transistor but was slow in comparison (especially going from high to low) and needed multiple power rails. This was replaced by NMOS, which was faster, simpler to design and could use a single power rail. PMOS and NMOS both used a single transistor and a resistor in a pair (NMOS could use a second transistor configured as a resistor, but the idea holds), so one of the two states was always drawing current. CMOS uses a complimentary pair of transistors, one PMOS and one NMOS. When the state changes one transistor turns off and the other on. Current flows only when the state is changing (in theory at least) as the transistors are partially on or off.
The 6809 used a pair of clocks, one of which was 50% out of phase with the other (i.e. the second clock changes half way through a 1 or 0 state of the first). To generate this phase difference it needed a crystal that was 4 times the fundamental frequency of the CPU, not a 4 phase clock. The E version of the 6809 used an external clock and you can see the two clocks documented there (E and Q).
I got a couple things to point out.
First, your two-relay SR latch actually has the outputs on the outputs of the OR gates/inputs of the inverters, which is the opposite of the logic diagram. (That's fine, though, since it just means the Q and Q-bar outputs end swapped. This matches how they appear on the actual schematic involving relays, so no problems are introduced by this.) This was actually the case in the last couple videos; I just didn't notice it before. It does unfortunately make it hard to represent what's _actually_ happening in your circuit (rather than an approximation) with NOR gates, though.
Second, the gated SR latch you actually built has the OFF and common terminals for the SR latch portion swapped compared to the schematic. That's not a problem right now since you aren't using the ON terminals on those relays currently, but there's the possibility it may cause problems for future expansion.
You must have eagle eyes to spot that common and off were swapped, but functionally it doesn't make any difference and i wanted to show the race conditions. Unfortunately, there can be a big gap between filming the circuit and making the video which means sometimes errors like this creep in.
For example, I'm currently building/filming and debugging the program counter for the relay6502, but I'm several (5+) videos behind in the production.
Very nice explanations, very educative with pinch of practice, excelent !
Glad you liked it!
@@DrMattRegan I learned in times where was no Internet or not i this form. I learned from book of German autor before I ended primary school. I known about 90% 74 series TTL from memory ;)
Great explanations. Not sure if you need to fall back to relay logic equivalents anymore though, You've made it pretty clear I think as is.
Cool, thanks for the feedback!
I'm thinking of splitting the series after two more videos.
I'll move into semiconductors (7400 series, SRAM, EPROMs etc) in one
stream, build the alarm clock, then Turing machine and make it 6502 compatible. This will be the more educational stream.
In the other stream, I'm going see if i can take the relays all the way to a relay 6502. I just need to get to the d-type flip-flop and ripple counter in the current series. It will force me to make a more efficient sequencer.
@@DrMattRegan oh wow, that'd be some project. Looking forward to all that.
Yeah, should be fun. Simulations work for a 250 relay decoder, we'll see how it goes.
But relays are so much more fun and satisfying. All that clicky goodness.
nice video
Thanks, enjoy!