@@ComponentByte Here in 1st Example Matrix [2:0] [3:0] You have taken left one as row and right one as column But in 2nd example You have taken oppositely Why? What's the difference between these both Matrix [2:0][3:0] Reg[2:0] mem[3:0] Is both same?
Matrix [2:0][3:0] is a vector having 3 rows and 4 column. After name indicates , 1st one is row and 2nd one is column I.e. how many rows and how many column REG [2:0]mem[3:0] has 4 rows and and each row has data of width 3 bit.it doesn't have any column. Before name indicates the data getting stored will be having how many number of bits Both are not same.
I was thinking to make Basics of System verilog but due to unavailability of proper simulator tools and shortage of time , now difficult to make tutorial on said topic. But for System verilog you can always take help of www. testbench.in website.Thanks.
sir, thanks for the lecture series....in the above video reg [2:0] mem[3:0] must be representing an array of a row containg 4 blocks with each block containing 3 bits of data,but u have mentioned it as 3x4 2-D matrix. This is according to my understanding. please correct me if i am wrong.
Hello, can you please mention the timing here because I couldn't find those words. If I have said so then definitely it's not 3x4 matrix. It can be 4x3 matrix as 4 rows with each 3 bit. I appreciate every individual's learning when someone finds any mistakes in my explanation or content. Yes ,your understanding is absolutely correct .Thank you.
@@ComponentByte thank u sir for ur fast response.if it is possible could u make vedio on divided by 5 nd 7 by using flip flop and mod counter.i saw many vedios on utube but it's not up to Mark but if u explain it then many of them will understand easily.Thanks for ur kindly gesture on students may God richly blesses ur work.
sir thankyu for yur great efforts but could yu please make a video on the tools available open source? ModelSim is commercialised and students like us could not afford sir
email2vesystem@gmail.com If you want you can share with me your number in the given email id and I will call you. This is the only way people contact me for their query.
You are correct,Wire can't store. What the statement means it's a vector net that you know already. may be this is the only video where it has been mentioned that wire stores which is not true. Please watch my reg and wire tutorial to know the difference between reg and wire. If those lines confused you then I am really sorry . It's my mistake. I appreciate your learning.
In previous videos we haev learnt that wire doesn't store any values and reg stores value but here wire a stores a bit . I don't understand sir please explain
Wire is like a connection or path between two terminals so it just allows data to pass through it so all terminal or port names(input and output as this is connected to some other terminal) are by default WIRE. Reg is like a storage or Register , so it stores data either 1 or 0. If output port stores data before it passes to other terminal then declared as REG. You can watch my VIDEO on REG and WIRE to learn more about it.
@@ComponentByte At 3:34 we see that (written in red) wire is storing bit.. But in earlier video you told that wire doesn't store any bit ... Please clear this doubt .....
reg and wire tells how an object will be assigned. If you assign value to reg variable then it stores that value , so basically creating register hardware to store that value.(eg:counter) If you assign value to wire variable then it cannot store or hold that value but yes that value is assigned , so basically here we are creating a electrical path and not a Register. assign statements (used for wire) create a port/connection reg statement creates a Register. Think it interms of hardware wire a; Here we are creating a port or connection wire [3:0] a; Here we are creating 4 port or connection reg [3:0] a; Here we are creating a register with 4 flip flops
could u explain this in briefly it means , how many rows & columns it were contained reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional array
2D contains row and column so here 16 row and 8 column. 3D is a cube means combination of 2D array. So here 8 number of 2D array which contains 16 row and 8 column 4D is how many number of 3D or cubes. So here 256 number of Cubes or 3D which has 8 number of 16 rows and 8 columns. All the data are of 64 bits. I am not sure whether I could make you understand or not.
Thanks for the wonderful lecture. Can i write a verilog code for storing coefficient of sparse matrix in ROM memory similar to the one you have explained here. eg. reg [2:0] mem[0:4][0:7]; initial begin mem[0][0]=2'd1; mem[0][1]=2'd1; mem[0][2]=2'd3; .... end
Welcome. You can always store coefficients in a textfile and then include the textfile where you have written your coefficients in either binary or Hex format on the top module. Please explore more about reading text file in verilog design. Hope this helps.Thanks
You can convert the decimal numbers into hex or binary using matlab tools. It's not that difficult. Because to my knowledge all the coefficient in verilog design are stored binary or Hex format. Even if the number of coefficients are more then also it won't be a problem.
Hi, I think you have forgotten to write port. Module without port gives such error. If you have not got it correct then you can send me the code. Thanks.
@@ComponentByte here is the code module Verilog( ); reg [8*28:0] string; initial begin string = "Hello verilog World"; $display("%s ",string); end endmodule
This is a testbench code. If you synthesize the above code then you will get error in xilinx because there is no any port declared inside module() . It violates the basic rules. I had compiled the code using modelsim software. So just check the testbench result in xilinx. Don't synthesize the code.
It's universal fact that wire is used for connectivity hence it gives Z(high impedance) and reg is used for storage(1/0) so it's value is unknown X by default.
Yes, wire can't store data. If I have said wire can store data then it's wrong(may be it's slip of tongue as I was new to making UA-cam video). Consider this as assigning value and not storing data technically. Sorry for the confusion. My intention is never to spread wrong information. Hope others get benifit from your comment. Thank you.
Wire can't store data. This is the ultimate truth. I have explained this on comment section. Please check it.sorry for the confusion. I am not a politician 😊that I will change my word. Thank you for pointing out the confusion.
12:10
In second example
Why it was written 4 rows 3columns
Why not in opposite way
From the 3 examples shown 1 and 2 are contradicting each other
Last line I am not getting what exactly you are asking. Please elaborate that contradicting part so I will be able to answer your first line
@@ComponentByte
Here in 1st Example
Matrix [2:0] [3:0]
You have taken left one as row and right one as column
But in 2nd example
You have taken oppositely
Why?
What's the difference between these both
Matrix [2:0][3:0]
Reg[2:0] mem[3:0]
Is both same?
Matrix [2:0][3:0] is a vector having 3 rows and 4 column. After name indicates , 1st one is row and 2nd one is column I.e. how many rows and how many column
REG [2:0]mem[3:0] has 4 rows and and each row has data of width 3 bit.it doesn't have any column. Before name indicates the data getting stored will be having how many number of bits
Both are not same.
3:39
reg[0:3] a; /* isn't the comment supposed to be from "rightmost" 3 to "leftmost" 0 */
Yes,Thank you for correcting the mistake. Really appreciate your learning. Thanks.
at 16:40 can't we initialize each blok of the array using loop?
like how we do it in c or c++?
Yes, possible
It's the best explanation.thanks
Please check FPGA made Easy youtube channel
Thank u so much sir...your videos are covering almost all points. 👌👌 Very helpful
You are welcome. Happy learning.
Sir can u also make such videos on system verilog and tcl
I was thinking to make Basics of System verilog but due to unavailability of proper simulator tools and shortage of time , now difficult to make tutorial on said topic. But for System verilog you can always take help of www. testbench.in website.Thanks.
wow, it's a great one.
Concept clear thanks
sir, thanks for the lecture series....in the above video reg [2:0] mem[3:0] must be representing an array of a row containg 4 blocks with each block containing 3 bits of data,but u have mentioned it as 3x4 2-D matrix. This is according to my understanding. please correct me if i am wrong.
Hello, can you please mention the timing here because I couldn't find those words. If I have said so then definitely it's not 3x4 matrix. It can be 4x3 matrix as 4 rows with each 3 bit. I appreciate every individual's learning when someone finds any mistakes in my explanation or content. Yes ,your understanding is absolutely correct .Thank you.
Sir can u tell which book(with good examples) should i follow for computer organisation and architecture.
And your videos are great.
Sir, I wish you were my teacher
Please check FPGA made Easy youtube channel
Wow, thanks a lot .
Thank you sir
8:34 sir, if data type is simply specified as reg , what we conclude sir whether it is vector or array?
Oh sorry 😅sir ,i understood that one
Sir, at 12:47 reg[2:0]mem[0:3] each cell is storing 3 bit or 1 row will store 3 bit?
In this example reg [2:0]mem[0:3], memory having depth of 4 means 4 rows and each row can store 3 bit.
r0---000
r1---001
r2---010
r3---011
@@ComponentByte thank u sir for ur response if coloumn is there then each cell in row stores 3 bit means a[0][0]=000 like that is it right sir?
reg[2:0]mem[0:3][0:4]
mem[0][0] , [0][1] ,[0][2] , [0][3] , [0][4]---all 3 bits
Same for other row and column.
Yes,you are correct.
@@ComponentByte thank u sir for ur fast response.if it is possible could u make vedio on divided by 5 nd 7 by using flip flop and mod counter.i saw many vedios on utube but it's not up to Mark but if u explain it then many of them will understand easily.Thanks for ur kindly gesture on students may God richly blesses ur work.
Definitely I will try to upload different logic to build different types of counter.
sir thankyu for yur great efforts
but could yu please make a video on the tools available open source?
ModelSim is commercialised and students like us could not afford sir
But you can always use xilinx and students version of modelsim. It's always available. Use online simulator edaplayground
@@ComponentByte okay sir
thank yuu
Sir do yu have a email id ?
it will be greatly helpful to ask more question sir
email2vesystem@gmail.com
If you want you can share with me your number in the given email id and I will call you. This is the only way people contact me for their query.
what is the meaning of integer [0:7][2:0] count; if we write ?
Each data is of size 3 bit and such 8 data's are there
1:18 wire can not sotre its passes value
You are correct,Wire can't store. What the statement means it's a vector net that you know already. may be this is the only video where it has been mentioned that wire stores which is not true. Please watch my reg and wire tutorial to know the difference between reg and wire.
If those lines confused you then I am really sorry . It's my mistake. I appreciate your learning.
In previous videos we haev learnt that wire doesn't store any values and reg stores value but here wire a stores a bit .
I don't understand sir please explain
Wire is like a connection or path between two terminals so it just allows data to pass through it so all terminal or port names(input and output as this is connected to some other terminal) are by default WIRE.
Reg is like a storage or Register , so it stores data either 1 or 0. If output port stores data before it passes to other terminal then declared as REG.
You can watch my VIDEO on REG and WIRE to learn more about it.
@@ComponentByte
At 3:34 we see that (written in red) wire is storing bit..
But in earlier video you told that wire doesn't store any bit ...
Please clear this doubt .....
reg and wire tells how an object will be assigned.
If you assign value to reg variable then it stores that value , so basically creating register hardware to store that value.(eg:counter)
If you assign value to wire variable then it cannot store or hold that value but yes that value is assigned , so basically here we are creating a electrical path and not a Register.
assign statements (used for wire) create a port/connection
reg statement creates a Register.
Think it interms of hardware
wire a;
Here we are creating a port or connection
wire [3:0] a;
Here we are creating 4 port or connection
reg [3:0] a;
Here we are creating a register with 4 flip flops
@@ComponentByte omg 😱😱😱😱😱 thanku soo much sir...
could u explain this in briefly it means , how many rows & columns it were contained reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional array
2D contains row and column so here 16 row and 8 column.
3D is a cube means combination of 2D array.
So here 8 number of 2D array which contains 16 row and 8 column
4D is how many number of 3D or cubes.
So here 256 number of Cubes or 3D which has 8 number of 16 rows and 8 columns.
All the data are of 64 bits.
I am not sure whether I could make you understand or not.
great! you should use graphic tablet, they are cheap and make your lectures better.
Thank you for your kind suggest but I know nothing about graphic tablet. I will try to explore the possible links.Thanks.
In previous videos it was said that wire cant store data in this video its being told that wire can hold data im confused if wire stores data or not
Wire can't store data. It drives data.
I have given the clarification on this same topic in comment section.
Sorry for the confusion.
Thank you!
Thanks for the wonderful lecture. Can i write a verilog code for storing coefficient of sparse matrix in ROM memory similar to the one you have explained here.
eg.
reg [2:0] mem[0:4][0:7];
initial begin
mem[0][0]=2'd1;
mem[0][1]=2'd1;
mem[0][2]=2'd3;
....
end
Welcome.
You can always store coefficients in a textfile and then include the textfile where you have written your coefficients in either binary or Hex format on the top module. Please explore more about reading text file in verilog design. Hope this helps.Thanks
@@ComponentByte Thanks for your reply..but if i have a large matrix with decimal value how do I read them?
You can convert the decimal numbers into hex or binary using matlab tools. It's not that difficult. Because to my knowledge all the coefficient in verilog design are stored binary or Hex format.
Even if the number of coefficients are more then also it won't be a problem.
@@ComponentByte ok.. Thank you for the inputs
Thank You very much for this generosity sir. I am having a problem while running it in xilinx with erro that module has no port. what is is mean?
Hi, I think you have forgotten to write port. Module without port gives such error. If you have not got it correct then you can send me the code. Thanks.
@@ComponentByte here is the code
module Verilog(
);
reg [8*28:0] string;
initial
begin
string = "Hello verilog World";
$display("%s
",string);
end
endmodule
This is a testbench code. If you synthesize the above code then you will get error in xilinx because there is no any port declared inside module() . It violates the basic rules.
I had compiled the code using modelsim software.
So just check the testbench result in xilinx. Don't synthesize the code.
Thank You sir
Welcome ! Wish you a happy learning.
DEFAULT value of wire is x and reg is Z, in last video it is wrongly given. Kindly correct.
You mean Default value of reg is Z and wire is X but I have given opposite in my lecture no- 4 tutorial. Is that true. Please correct me ?
@@ComponentByte yes
It's universal fact that wire is used for connectivity hence it gives Z(high impedance) and reg is used for storage(1/0) so it's value is unknown X by default.
I don't know which simulator you are using and how you are verifying all these concepts.
@@ComponentByte I also don't know the correct answer but on internet it is written so want to confirm it
bro in previous lecture u say wire cant store data.......but here u saying 3:40 wire can store data
Yes, wire can't store data. If I have said wire can store data then it's wrong(may be it's slip of tongue as I was new to making UA-cam video). Consider this as assigning value and not storing data technically. Sorry for the confusion.
My intention is never to spread wrong information.
Hope others get benifit from your comment.
Thank you.
@@ComponentByte pin comment
sir, is this not requires test bench code
Definitely I am going to make a tutorial for vector and array with testbennch.thanks for your comments
Is wire can store a value
No, wire is just a electrical path through which data flows.
Sir ,Is Wire can store data
No, wire can't store data. It's just an electrical path like a physical wire.
@@ComponentByte oh.. ok sir😊👍
In previous lecture u told wire caant store data but here youu chaange your words
Wire can't store data. This is the ultimate truth.
I have explained this on comment section. Please check it.sorry for the confusion.
I am not a politician 😊that I will change my word.
Thank you for pointing out the confusion.