Sir, in pulse can i give pulse width and period in ns and delay,falling, and rise time in ps. Then calculate delay. Sir, i am getting spikes in the output will i run at every failing and rising edge of input. How to remove those spikes
For single input and single output I got it. But sir in full ADDER circuit as we have 3 input and 2 output so how can I calculate average delay and power of circuit
Sir, when i am calculating half adder and full adder i am getting delay in ns but in the papers values are in ps. Can you tell how to reduce the delay from ns to ps.
Very helpful video sir. Thanku for explaining. Could you please also upload a video on temperature analysis in cadence virtuoso. That would be a great help sir
@@dr.hariprasadnaikbhattusir, SV university, Tirupati..... In mtech I did project on Low power VLSI... On HSPICE.... I want research topics in low power vlsi Or vlsi related topics sir
Sir I want to calculate delay for level shifter,in placing marker I was confused whether it can be placed both input and output at rising or falling or one is rising and another one is falling could you please give response sir..
Hello Sir, While simulation, it's not opening outlog and waveform but it show successfully running in virtuoso window Can I know what has to be change in setting??
this was very very helpful! i am in UCLA right now and your impact sir is global. Well done for the clear instructions.
Thanks for your support
The world's best teacher thanks sir
Thanks for the appreciation
This was hugely helpful to do my lab. Thank you.
Glad it was helpful!
Sir, where can i take the capacitor
As per my knowledge you can take it from the library "Analoglib" (please correct me if I am wrong)
@@c-jay1014 thank you I will check sir
@@r-rr3gn my pleasure
Hi, some one answered
@@dr.hariprasadnaikbhattu sir did I say correct ?
Sir, in pulse can i give pulse width and period in ns and delay,falling, and rise time in ps. Then calculate delay.
Sir, i am getting spikes in the output will i run at every failing and rising edge of input. How to remove those spikes
Hi, First question answer is OK and calculate delay.
Second check the supply voltage.
Very nice explanation! Thanks a lot!
Thanks and Welcome
For single input and single output I got it. But sir in full ADDER circuit as we have 3 input and 2 output so how can I calculate average delay and power of circuit
Full adder has three inputs. To calculate the delay any one input is sufficient either A or B or C.
Sir can i give in vpulse and vdc specification in terms of nano instead of pico.. So if i gave in nano it will gave the same?
I'm it will gave propagation delay?
Hi, vpulse can be in nano second but vdc has to be V
It can give delays
Ok tq sir
@@SIEC_KUSUMAHS welcome
Sir, when i am calculating half adder and full adder i am getting delay in ns but in the papers values are in ps. Can you tell how to reduce the delay from ns to ps.
Sir I want to calculate delay of full adder circuit and average power of full adder in Cadence virtouso
You explained very well sir. Can you explain how to calculate group delay in cadence tool, it would be very helpful.
Hi
Check for groupdelay in calculator special functions
@@dr.hariprasadnaikbhattu Yes sir, Thank You.
Sir how to remove those spikes in output???
Which spikes are you talking about.
At the transition from 1 to 0 and 0 to 1 of output
Hello sir. its a very helpful video.. For 4:1 MUX circuit how to find the delay? in cadence?
Hi, delay calculation is same. Consider any 1 input and 1 output. Find the delay. Have a video on it watch it
how to calculate delay for NAND GATE??
Process is same. Consider vin = a or b and vout =y
Very helpful video sir. Thanku for explaining. Could you please also upload a video on temperature analysis in cadence virtuoso. That would be a great help sir
Hi, Thanks for your response.
Definitely I will post a video on that.
Where can i find the theory behind delay sir
Yes , please help me 😢
Hi, there are many articles on this find it on google
Hi, there are many articles on this find it on google
Sir do the manual calculation and by using calculator(tool) delay differs ?
I have showed the Tool Procedure.
Sir could please suggest few research topic in antenna
SIW antenna
Can u show the delay calculation for a coomparator sir?
Comparator is analog design. Need to check.
@@dr.hariprasadnaikbhattu
Sir will u provide your mail id?
I am watching your layout video and practising for inverter sir
@@BrindhaThanjavur you provide your mail id
Sir, I am research scholar in VLSI, please suggest research topics in VLSI, how can contact u?
Where are you working. What is your specialization in VLSI.
@@dr.hariprasadnaikbhattusir, SV university, Tirupati..... In mtech I did project on Low power VLSI... On HSPICE.... I want research topics in low power vlsi Or vlsi related topics sir
Sir I want to calculate delay for level shifter,in placing marker I was confused whether it can be placed both input and output at rising or falling or one is rising and another one is falling could you please give response sir..
Hi, delay is always between the input and output.
Thank you kind sir. Bless your heart. 🙏
Thank you 🙏
Hello Sir,
While simulation, it's not opening outlog and waveform but it show successfully running in virtuoso window
Can I know what has to be change in setting??
Restart and check.
See the ADE window for output enabled or not.
Thank you so much!
You're welcome!