DVD - Lecture 6b: Multiple Voltage Domains

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 6 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 6 covers the traversal from the logical domain of RTL and Synthesis to the Physical Implementation stages of Floorplanning, Placement and Routing. This lecture focuses on Floorplanning, including Power Planning and a bit about Multi-Voltage and Hierarchical design.
Lecture 6b provides a brief introduction to the concept of multiple voltage domain design, power gates, CPF/UPF, and low-power design in general.
Lecture slides can be found on the EnICS Labs web site at:
enicslabs.com/...
All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[@Elior92]

Hi Adi,
First of all. Love your courses and I owe you great deal of my career :).
One question I have about power gating - The said switches that control the VDD should be at the lower layers of the silicon right? i.e , same layers as all the standard cells.
Does it mean that current has to travel all the way down to the bottom layers, pass the switch (in case it is open) then climb back up for the secondary (gated) power grid?
if so, doesnt that consume too many of our routing resources (since we now have two power grids in at least one routing layer)? that makes it very inefficient.
Thanks!
Elior.

[@AdiTeman]

Hi Elior,
So I don't go very deep into power gating in this lecture. It is quite a complex subject, but in general there are a few approaches and it does get tricky. The power gates are, as you said, just transistors on the bottom layer. The power grids do go over the entire area and they go up to higher layers. But this is where various strategies of power planning come in.
I actually have a more detailed (though also high level) explanation in this lecture at around 48 minutes ua-cam.com/video/TKfV73i-0RY/v-deo.htmlsi=T0AnoGAsVPJMF8fX&t=2910
In general, you could power gate each standard cell row and then just deliver the power through the PG pins (M1) or you could put a ring of power gates around the domain and then deliver power through stripes above the domain - using as many stripes as needed to achieve sufficient EM/IR. But if you also have always-on gates in the domain, you have to supply them separate power routing, so this gets tricky.
In any case, it's a good question and you need to provide as many power gates and as much power routing as necessary to sufficiently feed the transistors in the domain and this eats up routing resources. Watch the lecture I linked to before - there is a lot more to this (and I hope to provide an improved lecture later this year).

[@Elior92]

​@@AdiTeman Thank you very very much for the elaborated reply :)
I will look into the lecture you referred to, I took a glance at it an it seems to cover this topic pretty well.