Power Gating and Mother/Daughter cells in VLSI

[@merrygo7189]

I shared your video ...hope you will get more subscriber.....

[@jairamgouda]

Thank you so much 😀

[@charyvadla4486]

Thanks a lot

[@someshch5620]

Thank you

[@merrygo7189]

Thanks 👍 a lot..

[@jairamgouda]

Most welcome 😊

[@AnimeshVaishees]

short circuit power doesn't come under static power leakage

[@AhmedCr]

I agree, short circuit is part of dynamic not leakage power

[@himansh1308]

Sir, how to decide the number of power switch in header/footer??

[@CADDD_ACADEMY]

Bro PMOS is slower than NMOS. PMOS has higher delay compared to NMOS! If aspects ratio (W/L) is constant

[@hahtesham11]

PMOS is slower device than NMOS considering same W/L .because holes have less mobility than electrons. NMOS has faster discharging .