Thank you very much! This is the best explanation and complete demonstration of how axi stream interface works! This is invaluable for my university studies.
Thanks for your work ! It really helps me to understand HLS ! I just have a question about the MEM_BASE_ADDR on the Xilinx SDK, is 0x01000000 an arbitrary value ? Does 0x00000100 would have worked ? How am I supposed to choose this value ?
This might be an outdated question but I am intrigued by something. I've always wanted to use the AXI Stream the same way we use a AXI Lite. What I mean is, declaring an input and an output stream with an arbitrary precision data type and then specify to the synthesizer that both are AXI Stream interfaces, via #pragma. My objective is to basically get rid of the signal handling of the AXI Stream (driving KEEP, STRB, LAST, etc...). Is that possible? Thank you very much in advance! Julian
I had a really hard time finding the source code that the instructor says he shared at the end of lessons. It is hidden in the video "Playlist" description. For people who are looking for the source code here it is drive.google.com/drive/u/0/folders/0B4pAjkOvvOqJfnVjUkVKNURPMnozTVdUaFBBcVYtTExrNE5mVUtzOHZKVWJ0aUt4YllOamc Great lessons for kick starting the HW/SW desgin projects. Kudos
Thank you for the in-depth tutorial on using axi stream and DMA! I went through it on the Pynq-Z1 board and made the project files available here: github.com/smosanu/axi_stream_tutorial
Hello sir, I am doing the same code as u have explained in this video. But while writing the hls code(core.cpp) , i am getting the error as "valOut is not declared". But when i just copy pasted your code that u have given , it is running. I have written same code as u did. What must be the issue?
Hi Can you please share the core.cpp ? It's a little hard to read the comments off the video. Or, if there is a pdf with these example, can you point me to them? Thank you!
+ladygreenlife check his last video in this tutorial series (VIVADO HLS 2D Convolution on hardware part 3). Link for all tutorial files is in the description.
In the link, I am not able to find main.cc (sdk code) for lab7 (above video) drive.google.com/drive/folders/0B4pAjkOvvOqJfnVjUkVKNURPMnozTVdUaFBBcVYtTExrNE5mVUtzOHZKVWJ0aUt4YllOamc
Can you guide me how i can measure the time for writing to DDR and reading from there?? Actually i am getting some thing by using Axi_timer ip but when program gets enter in interrupt handler function and comes out it shows same time as before entering to handler. Waiting for your nice reply. Regards
Hello, Thank you for the video tutorials. They are quite informative. I tried implementing the above design. I get error when I try to generate bit streams. The error is regarding IOStandard and Package Pins. The IO pins are not placed. Can you provide a constraints file or explain placement constraints or provide a link where I can get help. I used LVCMOS12 IOStandard. I need help in understanding how to decide a pin number for IO port ( example: package pin for outstream_TDATA[1]).
Thank you very much! This is the best explanation and complete demonstration of how axi stream interface works! This is invaluable for my university studies.
Great video, that would be prefect if you could post the code. But anyway, that is good process to retype the code and learn it.
Obrigado. Foi uma boa explicação sem complicações
Thanks you and congratulations for this incredible tutorial !
Thanks a lot for the tutorials. It's been very helpful to me.
You are a great resource. Outstanding.
Thanks for your work ! It really helps me to understand HLS ! I just have a question about the MEM_BASE_ADDR on the Xilinx SDK, is 0x01000000 an arbitrary value ? Does 0x00000100 would have worked ? How am I supposed to choose this value ?
This might be an outdated question but I am intrigued by something.
I've always wanted to use the AXI Stream the same way we use a AXI Lite. What I mean is, declaring an input and an output stream with an arbitrary precision data type and then specify to the synthesizer that both are AXI Stream interfaces, via #pragma. My objective is to basically get rid of the signal handling of the AXI Stream (driving KEEP, STRB, LAST, etc...). Is that possible?
Thank you very much in advance!
Julian
I had a really hard time finding the source code that the instructor says he shared at the end of lessons. It is hidden in the video "Playlist" description. For people who are looking for the source code here it is drive.google.com/drive/u/0/folders/0B4pAjkOvvOqJfnVjUkVKNURPMnozTVdUaFBBcVYtTExrNE5mVUtzOHZKVWJ0aUt4YllOamc
Great lessons for kick starting the HW/SW desgin projects. Kudos
thanks, I am tryping the code and many times small mistakes lead to lots of confusion, though typing is good for better grasping
i wrote a message hi to access the code
Hey, I'd like to use it but it says I need permission
why main.cc ? it is supposed to be main.c in Eclipse SDK @25:17
You can select C++ while creating application project
why dont we need ap_axis in AXI master that is also stream. ?. in video 9 named Vivado HLS Training AXI Master
Thank you for the in-depth tutorial on using axi stream and DMA! I went through it on the Pynq-Z1 board and made the project files available here: github.com/smosanu/axi_stream_tutorial
Thank you so much
Thank you so much!
Hi, do you have code for other videos aswell ?
@@Shahidsoc no, just this one or a few
@@SergiuM Thank you for reply.
Hello sir,
I am doing the same code as u have explained in this video. But while writing the hls code(core.cpp) , i am getting the error as "valOut is not declared". But when i just copy pasted your code that u have given , it is running. I have written same code as u did.
What must be the issue?
How to do the same thing for 2D matrices as input for IPs like SVD and Matrix multiplication?
When I have launched my SDK, testAxiStream and testAxiStream_bsp files are not there? Can someone please help me out here.?
Very usefull!
Hi Can you please share the core.cpp ? It's a little hard to read the comments off the video. Or, if there is a pdf with these example, can you point me to them?
Thank you!
+ladygreenlife check his last video in this tutorial series (VIVADO HLS 2D Convolution on hardware part 3). Link for all tutorial files is in the description.
In the link, I am not able to find main.cc (sdk code) for lab7 (above video)
drive.google.com/drive/folders/0B4pAjkOvvOqJfnVjUkVKNURPMnozTVdUaFBBcVYtTExrNE5mVUtzOHZKVWJ0aUt4YllOamc
Here is the Code github.com/reigngt09/VivadoHLS/blob/master/HLS_Tutorials/HLS_Streaming.cpp
@@bellicose2009 can you please share the link to BRAM_INTERFACING main.CC(SDK SOURCE ) code also
Can you guide me how i can measure the time for writing to DDR and reading from there??
Actually i am getting some thing by using Axi_timer ip but when program gets enter in interrupt handler function and comes out it shows same time as before entering to handler.
Waiting for your nice reply.
Regards
Hello, Thank you for the video tutorials. They are quite informative. I tried implementing the above design. I get error when I try to generate bit streams. The error is regarding IOStandard and Package Pins. The IO pins are not placed. Can you provide a constraints file or explain placement constraints or provide a link where I can get help.
I used LVCMOS12 IOStandard.
I need help in understanding how to decide a pin number for IO port ( example: package pin for outstream_TDATA[1]).
No video can tell us how to match RTL design's address with C driver's address. Shit.