Thank you for this video . You touched on main very essential noise issues that are rarely found on youtube tutorials. Plus you brought up the issue of noise in ground which others fail to clearly highlight.
Thank you for this explanation. I have a question: At 7:43 why did you draw the return path of the current (green line) like this: From the Source of the MOSFET up to the Drain (vertical line) and then a diagonal line straight to the left (shortest way) to the negative power source connector of the circuit. After your explanation I would assume the current would return right underneath the upper trace on the WHOLE way back right to the postive power source connector on the left and only then "go down" to the negative power source connector since you said the two paths of the current attract each other. Did I miss something?
You have a keen eye and a good question. And the answer: the attraction between the current is frequency dependent. The current of the transistor is a short pulse containing high frequency components and hence the attraction. The current of the inductor stays about constant so there is little attraction. But again, not many catch these fine points as you did.
@@sambenyaakov Wow. Thank you for your fast answer. I wonder if I understood you correctly: What you are bascially saying is that the attraction of the currents is only high near the transistor due to the fact that the switching of the transitor is the source of the high frequency components of the current (high slew rate). As we have learned in your video the ground plane (or any PCB trace) also behaves like an distributed inductor for high frequency components and thus - if i am correct - must also act as a filter for these components and the attraction gets lower and lower? Would it be correct to say the attraction of the currents decreases with the distance to the source of the very high frequency components of the current? Sorry for all my questions :)
Hi professor, thanks a lot for your excellent videos! For Point 6, I noticed some experts suggest to NOT divide the digital ground with the power or analog ground. I prone to think that way too. if the signal lines go across the gap, the return path would be squeezed to the narrow connection point, not only enlarging the return area, but also entanged with each other to produce a noisy gournd point.
Thanks for comment. I am sure you are not suggesting to mix digital and power devices all over the board?😊 Clearly, you have to group each type by itself. So you end up with two separate areas. The interface could take different shaped depending on system. The illustration in the video is just to emphasis the need for separate areas.
Just want to say thank you, Professor Ben Yaakov. I've bumped into your channel a few days ago and it's a real gold mine for a grad student -or for anyone to learn power electronics-!
Dear Prof. Benyaakov, I just want to say thanks for a nice direction that you gave me few years ago regarding flyback transformer as clamp snubber circuit. Your guidance was so effective for my thesis defense and papers. I hope to see you someday.
This is an impressive collection of knowledge. Every point you made were the same ones my mentor drilled into me. He was in aerospace as a power electronics EE and a lot of this is tribal knowledge (it's not secret, it's just not many people know about it unless you work in the profession). It's all available in bits and pieces in PDFs on the net, but only if you know what your looking for. Your presentation is excellent.
Thank you so much for this very useful lesson! Despite obvious physics behind, there are still so many mistakes in layouts even if you know this for many years. I implement approach, where digital and power parts are drawn on left and right side of the schematic, avoiding overlapping (usually you have bridge, filter, controller, driver, power stage etc, but it is much easier to avoid mistakes if controller and driver are not drawn in between of power elements).
I am a young self-taught electronics inventor, your videos been very insightful. the same topic on academia paper sounds complex, your's is great. I have build couple of 20A capable FET h-bridge drivers
Beginning at 10:45 : You talked about not connecting those two _grounds_ since that would result in current flowing. Now, what I'm wondering is: What should I do about the capacitive effect occuring at those two grounds?
Of course, these should be as small as practical, but in most cases the effect is negligibly small unless extremely high frequencies are processed. In these cases you may need guard planes.
Thank you so much !! I have been struggling to understand grounding for 3 years of electronics classes, and you just clarified it in 25 minutes ! Simple yet very precise and interesting video, this is excellent !
Thanks Professor. I’m from Chile and i want to know how to create a good pcb design, i want to be a good electronic designer. Thanks for this and all of your videos 👌🏼😊👍🏼
Dear Professor Ben-Yaakov, this is a fantastic video. Thank you! I have a question regarding your interpretation of the path of the return current (8:55 in the video). With the direction of the current "I" in the top trace from left to right (as shown in the video), the direction of the magnetic flux density (B) on the bottom plane shall be along the plane, directed upwards (right hand thumb rule). With the direction of the return current in the bottom trace being opposite to the current in the top trace ("-I"), this would mean that the direction of force acting on a (positive) charge on the bottom plane would be F = -I x B which will be directed _outward_ from the bottom plane, i.e. going "into the Video". With this logic, I am unable to see why the current in the bottom plane would allign itself with the top trace (9:13). A similar situation is shown in highschool physics examples, e.g. hyperphysics.phy-astr.gsu.edu/hbase/magnetic/wirfor.html#:~:text=Note%20that%20two%20wires%20carrying,currents%20are%20opposite%20in%20direction. In the situation of the video, the currents in the two parallel wires would be opposite, which would imply, by this logic, that they exert a repelling force on one another. Could you kindly share your chain of argument regarding this issue?
Thank you for this very intersting video. With more than 30 years of experience in designing PCB, I was aware of a number of problem that you explain. Now I'm trying to mix a mosfet driver, with a part with sometime sharp arc sparks. Is there any way to mix mosfet (low impedance driver) with sometime very high voltage ? This is a mix of high current, high frequency and high voltage. It's very challenging !
@@sambenyaakov I would like to send a pulse with a Mosfet bridge through a toroid transformer to a high voltage (2500V) DC supply. In that way, I would like to test wire with problem. With the pulse there will be a spark, if the break down voltage on the wire is reach. The problem with high voltage and capacitor is the amount of energy in cas of spark. I tried to reduce the capacitance on the line, but it's still difficult to avoid large spikes on the Mosfet side. That's why I said mix. The sparks are very strong and can distroy all active components. I need a way to protect the Mosfet against spikes. TVS, transil, gas arrester, etc .. Or may be just a smart circuit :) Your advice and your practical approach are very usefull. I have already used your teeching for the snubber on the Mosfet, that works perfectly. I'm very thankfull.
Hi Professor. For more than one year I have been attempting to replace the drive of my 6kW 48V inverter without long term success. Originally it was derived from a, now broken, processor. The Chinese manufacturer would not supply replacement parts. I am using an EGS002 which has its own procesor & IR2110 to provide hi & lo level drives for my SPWM full bridge. You mention not needing such a fast drive for 20kHz, my fast side is 24kHz. The recommended circuit has fast turn off diodes accross each series gate resistor. Might I have less blow-ups by removing these? Further to Infineon application note DT97-3 I reverted to fully floating stabilised supplies. Have now added PNP/NPN buffer stages local each of my MOSFET banks, 6 paralled IRFB4310 & attempted to observe your grounding rules. Also, as per your recommendation, I have fitted Fe beads to each MOSFET gate lead. Thank you for your very helpful clear & understandable lectures. Dave Johnson
Another really informative video, many thanks for sharing your expertise. Do you have any observations to make about wiring equipment cabinets? I would be interested to hear your thoughts on power distribution, earthing connections for motor drivers, locations of ferrites and EMI filters, choice of 3 or 4 core cable for motor, cable screening connection points, etc.
Thanks for comments. Will try to cover some of the subjects you pointed out in the future. Meanwhile scan my UA-cam videos for relevant presentation e.g. ferrites
Again an excellent video. Thank you professor, One question came to my mind, I'm always generating gate drive circuit's power on the let's say DGND part and route it to the gate driver IC (that is on the PGND part) over the narrow GND copper. Is this the right way or should I generate the power at PGND side? (by the way I'm not using isolated gate drive - because of the cost down issues)
Prof. Sam i have a question, for the ground plane there is alot of branches connected on it. Are the current will interference on each other and the paths will be chaos? How to model these behaviors mathmatics andwhat is the keywords of what iam talking about? Thanks for your content 🌺🌺
Problems will arise if you have both high power and low power (control) sharing same ground plane. If you separate there is no issue of "chaos". There are many application notes that describe layouts.
Thank you sir for the great explanations, but i have doubt (in #4) that if the current of parallel wires flows in opposite directions then they tend to repel each other but you are saying opposite, why sir?, kindly clear it...
Thank you for this video . You touched on main very essential noise issues that are rarely found on youtube tutorials. Plus you brought up the issue of noise in ground which others fail to clearly highlight.
Thnks for review
Thank you Professor. Just what I wanted, I just started my PCB designing a week ago. It clarified what I had been looking for.
Thanks for comment😊
Thank you, Dr. Ben-Yaakov, for your insightful videos and dedication to explaining even the smallest details. Your efforts are truly appreciated.
Thanks for kind note
Thanks for the awesome videos. I am studying power electronics at university but this is stuff they simply don't teach.
👍
Thank you for this explanation. I have a question: At 7:43 why did you draw the return path of the current (green line) like this: From the Source of the MOSFET up to the Drain (vertical line) and then a diagonal line straight to the left (shortest way) to the negative power source connector of the circuit.
After your explanation I would assume the current would return right underneath the upper trace on the WHOLE way back right to the postive power source connector on the left and only then "go down" to the negative power source connector since you said the two paths of the current attract each other.
Did I miss something?
You have a keen eye and a good question. And the answer: the attraction between the current is frequency dependent. The current of the transistor is a short pulse containing high frequency components and hence the attraction. The current of the inductor stays about constant so there is little attraction. But again, not many catch these fine points as you did.
@@sambenyaakov Wow. Thank you for your fast answer. I wonder if I understood you correctly:
What you are bascially saying is that the attraction of the currents is only high near the transistor due to the fact that the switching of the transitor is the source of the high frequency components of the current (high slew rate). As we have learned in your video the ground plane (or any PCB trace) also behaves like an distributed inductor for high frequency components and thus - if i am correct - must also act as a filter for these components and the attraction gets lower and lower? Would it be correct to say the attraction of the currents decreases with the distance to the source of the very high frequency components of the current?
Sorry for all my questions :)
@@ToBeDefined85 The inductor line carries basically DC with some ripple. The return of the DC component is distributed evenly in the ground plane.
Hi professor, thanks a lot for your excellent videos!
For Point 6, I noticed some experts suggest to NOT divide the digital ground with the power or analog ground. I prone to think that way too. if the signal lines go across the gap, the return path would be squeezed to the narrow connection point, not only enlarging the return area, but also entanged with each other to produce a noisy gournd point.
Thanks for comment. I am sure you are not suggesting to mix digital and power devices all over the board?😊 Clearly, you have to group each type by itself. So you end up with two separate areas. The interface could take different shaped depending on system. The illustration in the video is just to emphasis the need for separate areas.
Just want to say thank you, Professor Ben Yaakov. I've bumped into your channel a few days ago and it's a real gold mine for a grad student -or for anyone to learn power electronics-!
Thanks
Dear Prof. Benyaakov, I just want to say thanks for a nice direction that you gave me few years ago regarding flyback transformer as clamp snubber circuit. Your guidance was so effective for my thesis defense and papers. I hope to see you someday.
Hi siamak, thanks for heart warming comment.
Thanks professor Ben-Yaakov , very beneficial and well done presentation
Thanks for kind note
I just started my little journey from mostly digital design to analogue design and your channel is great! Thanks for sharing Professor.
Welcome aboard!
Thank you professor!
I awe your patience do dive into details and to explain each of them.
Thanks for taking the time to write this nice note.
This is an impressive collection of knowledge. Every point you made were the same ones my mentor drilled into me. He was in aerospace as a power electronics EE and a lot of this is tribal knowledge (it's not secret, it's just not many people know about it unless you work in the profession). It's all available in bits and pieces in PDFs on the net, but only if you know what your looking for. Your presentation is excellent.
Thanks😊
Very valuable information which is hard to see in books. Thanks a lot!
Thanks for comment
Thank you Sir, your explanation of the minimization of the loop inductance with frequency is one of the best that I have seen.
Thanks
Thank you so much for this very useful lesson! Despite obvious physics behind, there are still so many mistakes in layouts even if you know this for many years. I implement approach, where digital and power parts are drawn on left and right side of the schematic, avoiding overlapping (usually you have bridge, filter, controller, driver, power stage etc, but it is much easier to avoid mistakes if controller and driver are not drawn in between of power elements).
Thanks for sharing you experience.
I am a young self-taught electronics inventor, your videos been very insightful. the same topic on academia paper sounds complex, your's is great. I have build couple of 20A capable FET h-bridge drivers
Cool, thanks
Very well explained
Thanks
Beginning at 10:45 : You talked about not connecting those two _grounds_ since that would result in current flowing. Now, what I'm wondering is: What should I do about the capacitive effect occuring at those two grounds?
Of course, these should be as small as practical, but in most cases the effect is negligibly small unless extremely high frequencies are processed. In these cases you may need guard planes.
@@sambenyaakov Thank you, Sir!
Thank you so much !! I have been struggling to understand grounding for 3 years of electronics classes, and you just clarified it in 25 minutes ! Simple yet very precise and interesting video, this is excellent !
Happy to hear that. Thanks.
Thank you professor. Very useful information as usual. Greetings from New Zealand.
Thanks
Great video Professor!
Thanks😊
Thanks Professor. I’m from Chile and i want to know how to create a good pcb design, i want to be a good electronic designer. Thanks for this and all of your videos 👌🏼😊👍🏼
Thanks and greetings from Israel.
Dear Professor Ben-Yaakov, this is a fantastic video. Thank you! I have a question regarding your interpretation of the path of the return current (8:55 in the video). With the direction of the current "I" in the top trace from left to right (as shown in the video), the direction of the magnetic flux density (B) on the bottom plane shall be along the plane, directed upwards (right hand thumb rule).
With the direction of the return current in the bottom trace being opposite to the current in the top trace ("-I"), this would mean that the direction of force acting on a (positive) charge on the bottom plane would be F = -I x B which will be directed _outward_ from the bottom plane, i.e. going "into the Video". With this logic, I am unable to see why the current in the bottom plane would allign itself with the top trace (9:13).
A similar situation is shown in highschool physics examples, e.g. hyperphysics.phy-astr.gsu.edu/hbase/magnetic/wirfor.html#:~:text=Note%20that%20two%20wires%20carrying,currents%20are%20opposite%20in%20direction.
In the situation of the video, the currents in the two parallel wires would be opposite, which would imply, by this logic, that they exert a repelling force on one another.
Could you kindly share your chain of argument regarding this issue?
Hi, This has nothing to do with mechanical force but it is a result of the proximity effect. Look it up.
See ua-cam.com/video/E1_5HKnvFdY/v-deo.html&feature=share
Very helpful, thank you.
Thanks
Thank you for this very intersting video. With more than 30 years of experience in designing PCB, I was aware of a number of problem that you explain. Now I'm trying to mix a mosfet driver, with a part with sometime sharp arc sparks. Is there any way to mix mosfet (low impedance driver) with sometime very high voltage ? This is a mix of high current, high frequency and high voltage. It's very challenging !
Hi Thanks. Not sure I follow the meaning of MIX
@@sambenyaakov I would like to send a pulse with a Mosfet bridge through a toroid transformer to a high voltage (2500V) DC supply. In that way, I would like to test wire with problem. With the pulse there will be a spark, if the break down voltage on the wire is reach.
The problem with high voltage and capacitor is the amount of energy in cas of spark. I tried to reduce the capacitance on the line, but it's still difficult to avoid large spikes on the Mosfet side. That's why I said mix. The sparks are very strong and can distroy all active components. I need a way to protect the Mosfet against spikes. TVS, transil, gas arrester, etc .. Or may be just a smart circuit :)
Your advice and your practical approach are very usefull. I have already used your teeching for the snubber on the Mosfet, that works perfectly. I'm very thankfull.
Hi Professor. For more than one year I have been attempting to replace the drive of my 6kW 48V inverter without long term success. Originally it was derived from a, now broken, processor. The Chinese manufacturer would not supply replacement parts. I am using an EGS002 which has its own procesor & IR2110 to provide hi & lo level drives for my SPWM full bridge. You mention not needing such a fast drive for 20kHz, my fast side is 24kHz. The recommended circuit has fast turn off diodes accross each series gate resistor. Might I have less blow-ups by removing these? Further to Infineon application note DT97-3 I reverted to fully floating stabilised supplies. Have now added PNP/NPN buffer stages local each of my MOSFET banks, 6 paralled IRFB4310 & attempted to observe your grounding rules. Also, as per your recommendation, I have fitted Fe beads to each MOSFET gate lead.
Thank you for your very helpful clear & understandable lectures.
Dave Johnson
Another really informative video, many thanks for sharing your expertise. Do you have any observations to make about wiring equipment cabinets? I would be interested to hear your thoughts on power distribution, earthing connections for motor drivers, locations of ferrites and EMI filters, choice of 3 or 4 core cable for motor, cable screening connection points, etc.
Thanks for comments. Will try to cover some of the subjects you pointed out in the future. Meanwhile scan my UA-cam videos for relevant presentation e.g. ferrites
Thank you very much for the video.
Thanks for comment.
Again an excellent video. Thank you professor,
One question came to my mind, I'm always generating gate drive circuit's power on the let's say DGND part and route it to the gate driver IC (that is on the PGND part) over the narrow GND copper. Is this the right way or should I generate the power at PGND side? (by the way I'm not using isolated gate drive - because of the cost down issues)
See ua-cam.com/video/qkr6dtz5CdQh/v-deo.htmlttps://ua-cam.com/video/qkr6dtz5CdQ/v-deo.html
Thank you for knowledge.
👍😊
Prof. Sam i have a question, for the ground plane there is alot of branches connected on it. Are the current will interference on each other and the paths will be chaos? How to model these behaviors mathmatics andwhat is the keywords of what iam talking about?
Thanks for your content 🌺🌺
Problems will arise if you have both high power and low power (control) sharing same ground plane. If you separate there is no issue of "chaos". There are many application notes that describe layouts.
12:05 Attack on Titan
Thanks :)
👍
Thank you sir for the great explanations, but i have doubt (in #4) that if the current of parallel wires flows in opposite directions then they tend to repel each other but you are saying opposite, why sir?, kindly clear it...
See ua-cam.com/video/9RX-O2oollE/v-deo.html
Great explanation sir, I learned something new. Thank you sir 😊.
👍