Secrets of PCB Optimization - Rick Hartley - AltiumLive 2020
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- Опубліковано 2 тра 2024
- Many engineers believe the cost of both bare PC boards and assemblies is purely a function board size, thickness, number of layers, spacing between features, etc. Part of that statement is true, but certainly not all of it. There are many things driving cost AND quality of both bare boards and assemblies, things like ‘where’ the copper is located, as opposed to density, parts placements, how the board is routed, balanced PCB stack-up, feature sizes, etc.
This one-hour session will discuss how to accomplish the goal of both low cost and high quality, with just a few simple concepts. Bottom line, when boards are not designed properly, fab and assembly houses Must make modifications to the boards, just to be able to produce them. Sometimes their mods cause the boards to malfunction. If we design correctly, this will not happen. This workshop is intended for PC board design engineers, electronic engineers and system engineers, as well as technicians and managers interested in Cost and Quality of PC boards.
00:00:00 - Introduction
00:03:23 - Bare Board Fabrication, Critical Parameters
00:13:50 - Fabrication Report Card
00:15:45 - Panelization (Panel Sizes)
00:26:19 - Fabrication Panel Must Accommodate...
00:35:55 - Using an Assembly Panel for Small Boards
00:37:40 - Manufacturing a 4 Layer Board (Production Process)
00:51:10 - Thief Copper
00:58:36 - Coupons
01:03:00 - Various Processes (Etching, Multi-layer Pressing
01:06:56 - Number 1 Rule to Maximize DFM
01:10:28 - Things to Know and/or Ask PCB Fab or Assembler
01:14:20 - Good Design Rules for Narrow Traces
01:16:10 - Good Design Rules for Vias
01:18:49 - HDI/Microvia Technology
01:23:40 - PCB Assembly, Critical Parameters
01:25:00 - Conclusion
Speaker Bio:
Rick Hartley has over 50 years of industry experience focused on circuit and PCB design for computers, aircraft avionics, and telecommunications. After retiring from L-3 Avionics Systems where he held the title of Senior Principal Engineer, Rick started his own company RHartley Enterprises, through which he consults and teaches internationally to resolve EMI, noise, and signal integrity issues.
Rick has partnered with major corporations throughout the US and 14 other countries on projects involving medical systems, automotive electronics, and appliances. He's also taught seminars at various IEEE events, PCB West, Freescale Technology Forum, IPC Apex/Expo, AltiumLive, and a number of other public and private forums. Rick is a current member of the IEEE, IPC Designers Council Board of Directors and a past member of the Editorial Review Board for Printed Circuit Design Magazine.
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#Altium #PCBdesign - Наука та технологія
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Rick's voice is music to my years which directly touches my heart and brain at same time
Have you watched Breaking Bad / Better Call Saul? Because he sounds exactly like Mike Ehrmantraut. Who also sounds like music to my ears.
When Rick talks you just listen, he has a good way of communicating knowledge
Great presentation with an incredible amount of insight and knowledge. Rick is the best!
Well said, Rick. PCB manufacturers are not fairy grandmothers or genies that can do what you want. They have fixed capabilities and PCB designers must work within their ranges to keep the board prices as low as possible.
great content and great presentation.
very informative , thank u , you really change the way we think about circuit design , We want more !! :)
I designed numerous boards since 2013, I never used 4 mil traces! At least for the majority of boards, 9 or 10 mils works just fine and it is manufacturable by all manufacturers I have seen so far. I can not imagine how these guys used 4 mil traces for normal no HDI PCBs.
Amazing, just amazing!
Great interesting lecture by the Mike Ehrmantraut of PCB design.
Glad you liked it!
Thanks Rick.
Would you please make the slides available?
Hey Rick can we get a HD picture of your bookshelf?😂
I like this better. He reads all books and give us the summary 😊
Rupal M hahahahaha remembering high scool
nice
Why don't the fabricators create the thief dots for the plating process and then just etch them away later? It would still obviously be more costly and a sub-optimal design. Just trying to satisfy a curiosity rather than disagree with the overall message.
JLCPCB be pissing over all of this video
like it 👍
53:15 Eric Bogatin would argue that poring copper over the entire board is very silly. He claims (and shows with HFSS) that you get very little benefit from EMI and can easily make EMI much worse. When you have 2 of the biggest names in PCB engineering giving completely different answers it can be very difficult to know the correct solutions. In this case, I think Eric Bogatin has the correct information.
Eric and Rick are both correct in certain situations that do not always overlap. I've discussed why this is the case many times.
Eric's advice is technically correct but it's easy to take out of context. Copper pour is one of those things that is sometimes presented as an "always/never" type of guidelines. The truth is that it has specific uses that are grounded in impedance controlled design and it's one of those things that some people do blindly without understanding those specific uses.
@@Zachariah-Peterson I'm currently confused about the idea of uneven copper pour causing issues with the plating process. I already watched that part of the video twice. According to this very presentation, it seems like the pattern plating happens *before* the outer layers are etched? So isn't the full board always covered with copper when the plating happens? Or was the idea of avoiding uneven copper fill specifically about the inner layers? If it was then I completely missed that point twice...
@maruohon I don't have time to watch the entire video now so I'm not sure which part you are referring to. But I know that the uneven copper can apply to outer or inner layers. The biggest reason is symmetry across the center of the stackup to prevent warping, which is less to do with plating and would apply to outer and inner layers. I have seen instances where there are exceptions, such as when the board is small and only 1 of the layers has a lot of its copper removed. The resulting warping would be very small and would be within IPC specs.
Wow, PCB fabrication is more complicated than PCB EMC.
I have not seen an 18 by 24 inch panel the last 10 yrs...
He says he has 6 or 8 hours of content, then proceeds to give you 30 min of information in 1.5 hours. The stories and facts are great, but a lot of what he says is just repeating himself.