thank you, nobody explains how to draw these with preset and clear. one question can you do a problem that has those inputs on a jk flip flop. thank you so much
Q follows D at every rising edge of the Clock, not halfway. It only pays attention to D when the Clock is at a rising edge, after that it assumes the same value until the next rising edge at Clock. Hope that makes sense.
This was amazing, you didn't leave anything unexplained. Thank you.
I have an Exam tomorrow. Now, it is crystal clear!
Thank you for your clear explanation!
Glad it helped!
@@MandyTCTC I got that right!! Hats off to you🙏
Why can't teachers be as clear and concise as this lady?
you just saved my life! I could not figure this out for so long. but your explanation helped me so much! thank you!
Exactly what I needed thanks, Mandy!
You're a good teacher. Thanks Mandy Elmore.
thank you, nobody explains how to draw these with preset and clear. one question can you do a problem that has those inputs on a jk flip flop. thank you so much
Super helpful and intuitive video! Thanks so much.
Thank you for this, cleared it up for me.
just amazing
Wow this is nice work... Thank you so much
Great video
Holy god if my professor had just shown this video in class......
Really helpful video, thanks a lot
Glad it was helpful!
Wow thanks mate!
Thank you 🙏🏽
Thnx a lot :D
EXCELLENT
Thanks a lot!!
thanks so much : )
Thank you so much..
thanks !
I love you thank you
thank you so much mam.
Thx a lot :D :D
how do i connect the wires if i want to create a 3bit asychronous counter?
Holy Fuck! Thanks. Simple as shit.
How was the waveform generated please?
Nyc Vooice
appears timing period for preset and clear in shorter length than clock .
Hi what about if it was synchronous?
If Q follows D when PR & CLR are high. Why didnt the Q go down during halfway. In the early column
hasif salam yes I also felt the same
Q follows D at every rising edge of the Clock, not halfway. It only pays attention to D when the Clock is at a rising edge, after that it assumes the same value until the next rising edge at Clock. Hope that makes sense.
can we design a logic circuit using timing diagram??
Yes. Do you have one you want done?
Master slave SR waveform
this is not an asynchronous circuit because Q change according to clock isn't it?