Cache Mapping: Cache Initialization and Dirty Bits | L 33 | COA 2.0 | GATE 2022 | Vishvadeep Gothi

In this session, Vishvadeep Gothi will be discussing about Cache Mapping: Cache Initialization and Dirty Bits from the COA 2.0. Watch the entire video to learn more about Cache Mapping: Cache Initialization and Dirty Bits which will help you crack GATE CSE/IT 2022 Exam. Let’s Crack It!
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Start date: 25 Aug 2021
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#block, #replacement, #hit, #miss, #tag, #offset, #line, #address, #MainMemory #GATE2022 #GATECSE

[@rishukumar2325]

Home Work answer will be :- B). 151 and 137

[@AbhishekYadav-el7kc]

Best playlist I have ever encountered,love sir ❤

[@sangharshnagdevte5629]

God of computer architecture

[@DeadPoolPC999]

@UnacademyComputerScience Sir in 3rd question if we first calculate the tag and cache memory block bit than bits remain for offset is different : follows as cache memory size is 32KB & one cache block holds 32 bytes -> the no. of blocks =32 KB/32 B we got 1K as 2^10 ; 10 bit to justify cache address now as many blocks that many tags also present so same 2^10 tag registers then for each tag register 10 bits are sufficent . now if main memory is 16 MB and if 1 location stores 1B Byte addresable then no. of location becomes 2^4 *2^20(16M) so cpu genrates 24 bit main memory address and as result no. of offset bits left = 24-10(for cache block)-10(for tag identificaation)=4 bits left for byte offset and your caclulation is 5 bits sir i know you are calculating as block size =32 B so 2^5=32 so 5 bits sufficent to tell block address but see sir this block size you used belong to cache not the main memory the address which we broke down to identify tag,cache block address and byte offset. Then sir how could you confirm as both cache and Main Memory have equal size of block as that what you put in the solution @49:57 pls see and correct and do let me know also if i am somewhere wrong .Thank You

[@narayanchandra6180]

Really best playlist for COA❤💛

[@lazy7172]

@36:25
Sir here u r writing t in write back formula but in lecture 30 u wrote t ,why?
1 more thing
In case of miss a block will be brought from memory to cache ,we need to include cache memory block transfer time ?(As block transfer included formula in lecture 30 @17:30)
(Cache miss part of)Tavg should be = t + t + x* t ???

[@sarastemkar7835]

if miss we bring block to cache from mm in wirte back we accessin the block in cache then we writing it back to to main t block itself says its the time to write the block in main memory t is for time to access the block in mm not the tranfer only access thts why there it is written as tmm

[@godofphysics-physicswallah4071]

at 30:09 sir said that how we identify that which block from main memory is mapped to which block of cache memory is through Tag which is wrong as Tag is only used to check whether it is hit/miss but mapping is checked by cache memory block number which is of size 9-bits here.

[@Innov8mate]

@Unacademy Computer Science Thank you

[@sabbysays]

35:00 AMAT for write-back cache discussed

[@vivekkar7921]

sir in 37.14 how is the time for avg t read and twrite same as for read miss we have to transfer block from mm to cache , whereas in write miss transfer from cache to mm

[@MrSagarBiswas]

HW Q: only (B) is correct.

[@Emperor723]

thoda sa bata skte ho please kaise solve kia?

[@Officialnewone]

ready sir

[@abdulhameed1862]

Sir excellent

[@mayankrohilla4105]

Start 9:20

[@nit_shortz]

From where can i get notes for this playlist??

[@LordSarcasticVlogger]

start 59:50

[@sakshardas7828]

😂

[@competence9347]

36:14

[@mvenkataadityaprakash9485]

option b

[@vrishabh07]

19:38

[@gtxananth7742]

🤗🤗🔥🔥

[@swaroopsahoo214]

better ths gate applied cousre COA that too for free

[@ANUJSHARMA-ir6lu]

start 9:15

[@shubhamvarshney9626]

Start 7:49