Cache Write: Write Through & Write Back | L 30 | COA 2.0 | GATE 2022 | Vishvadeep Gothi
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- Опубліковано 12 жов 2024
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.. In this session, Vishvadeep Goth will be discussing about Cache Write: Write Through & Write Back from the COA 2.0. Watch the entire video to learn more about Cache Write: Write Through & Write Back which will help you crack GATE- 2022. Let’s Crack It!
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#cache, #spatial, #temporal, #LoR, #Hit, #Miss, #HitRatio, #Replacement, #Block, #AccessTime #GATE2022 #GATECSE
Amazing lecture from an amazing teacher 🥰
Start Time: 7:13
Thanks bro after seeing your comment i started the video at 7:13 🤣😅
Crystal clear concept with unique examples 😊
GOAT of COA
@24:27 If the given cache organisation is hierarchical the the formula of Tavg = hit*tcm + (1-h1) h2(t2+t1)
Answer for Question 1: 60ns
Answer for Question 2: 0.9
Answer for Question 3: 0.4
Answer for Question 4: 136ns
Answer for Question 5: 80.5ns
how 0.4 in question 3
Yes, all answers marched. Just q3 will have 0.4167 or 5/12
@@unknown-lv8io let cache access time be x, then memory access time will be 6 times cache time(given in question) i.e. 6x.
Now when memory is uncached then tavg will be just memory access i.e. 6x on the other hand when memory is cached then
Tavg = .7x + .3*6x i.e. 2.5x. Now for calculating ratio divide both we will get 2.5/6 or 5/12 or 0.4. Hope it helped
@@sakshardas7828 Bro how Q5 ans is 80.5ns, I am calculating it as 79ns. My end equation is Tavg = 0.9 * 15 + 0.1 * (15 + 8*80).
Pls explain.
@@shubhamagarwal5721 u forgot to add miss penalty, so ur eq will be
tavg = 0.9 * 15 + 0.1 * (15 + 8*80+15)
34:35 gajab example :)
Abhi tak 30 lecture attend Kiya apka concept acha hai
How can we use simultaneous access in case of write back??
Wouldn't it mean that the CPU sent write signals to both cache and main memory simultaneously. That means in case of cache hit, the signal going to main memory would be interrupted mid-way so that CPU could begin the next operation. That's why we only take Tcm as time in case of a hit.
Is this even possible to interrupt a signal like this mid-way??
Is BLOCK-SIZE differs , due to different configurations of R.A.M ( MAIN MEMORY ) on the basis of BYTE ADDRESSIBLE or WORD ADDRESSIBLE ?
7:00
Sir, Thank a lot
I can't say for your amazing teaching method😍❤️😍
Thanku Sir!!!!
Your way of teaching create mapping of concept. 😊🙏🏻
Thanks u sir ji for great playlist
Sir agar HIT nhi hua tabhi toh MISS hoga na , I guess 50 nsecs for each MISS for 1% , it would be counted along with the addition of HIT time or it would require 60nsecs overall hence AV ARAGE MEMORY ACCESS TIME would be 15nsecs instead of 14nsecs.
what if 3level is given? in 2004 there was a question with 2 cache and 1 main memory, it is 3 level hierarchy. what is the Tavg
formula for it?
best in the business
Great session 👍👍👍❤️❤️❤️❤️❤️❤️
SIR I GUESS AVARAGE MEMORY READ OPERATION TIME WOULD BE 150nsecs ,INSTEAD OF 500nsecs , BCZ AMONG OF ALL THE OPERATIONS WE GET 30% OF WRITE OPERATIONS ACCORDING TO THE QUESTION.
for HIERARCHIAL MEMORY ACCESS TIME for CACHE MISS we have to add MAIN MEMORY ACCESS TIME & CACHE MEMORY ACESS TIME ; hence the time would be (150nsecs+30nsecs=180nsecs)
This is accounted for when sir is using 30+(1-h)150=30*h+30*(1-h)+(1-h)150
homework question 3 kiya kaise hoga bro
@@prathamkumar3731 please take the MAIN MEMORY ACCESS TIME TWICE , to make the answer feasible.
Happy happy learning. ☺️🙂☺️🙂👌👌👌
amazing sirr
Where i can find pdf?
Thanks for such amazing lectures!
Great teaching way
value for investing time in watching this video sir
Great teaching sir
Thanks sir 😌
24:31 you missed H*Tcm
final answer will be 7/8
Koi question 5 bata do bro
Homework Q1: Ans Tp = 60ns
Homework Q2: Ans h = 0.9
Homework Q3: Ans --- didn't understand question
Homework Q4: Ans tavg = 19.2ns
Homework Q5: Ans tavg = 80.5ns
Q3 07:18 ratio of Average memory access time when Hit Vs when Miss
And also 4th Q 16ns it's hierarchy based system
bhai 4th ka 136 ns hoga
@@nirbhaykumarchaubey8777
Q3: let cache access time be x, then memory access time will be 6 times cache time(given in question) i.e. 6x.
Now when memory is uncached then tavg will be just memory access i.e. 6x on the other hand when memory is cached then
Tavg = .7x + .3*6x i.e. 2.5x. Now for calculating ratio divide both we will get 2.5/6 or 5/12 or 0.4. Hope it helped
@@nirbhaykumarchaubey8777 no bro Q4 ans is 136ns, We have to consider block size also since according to question it is specifically given in note that locality of reference is used so we have to transfer whole block to memory, for that we have to multiply 16 to memory access time considering memory is byte addressable. So the end equation will be like Tavg = 0.8*8 + 0.2[8(cache access) + 40*16(block access)]. On solving we get ans as 136ns, Hope it helped. Also correct me if i am wrong.
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At 32:25 😂😂😂