Hi, thanks so much for the video, it's really helpful! I've got a question: if the we've got a logic gate with a maximum fanout 3 and also give it 3 outputs A, B, C, the input-voltage for each of those three a third of what went into the gutter, right? If so, if we repeat this (So we connect for a example b to a not-gate, that fans out into the more than one outputs and so on) would the voltage eventually become too low in one of those outputs? Bc we've split it so often. I don't really understand the difference between what I just described or just a using more outputs than the maximum fan out, which you said results in too low voltage in the outputs.
Hi Rodriguez , thank you so much for asking question. Fan-out is measure of how much max capacitance, output can drive. Let say , AND gate is having max fan-out of 3 (say it can drive 3 pf capacitance) , and it is connected to three NOT gates (say A,B,C are 3 NOT gates) and so output of AND gate will drive 1 pf for each NOT gate . Now lets add extra NOT gate(input capacitance 1 pf) for the output of AND gate , since max fan-out is 3 , but we are adding an extra gate will result in slow change in output . Voltage will not be reduced. Slow change in voltage means : let's say at 1sec you required your voltage level to reach 1volts ,but due to slow change from the effect of extra capacitance at 1sec now the voltage will not reach 1volt ,it may reach at a later point say at 1.3seconds ,but that doesn't solve the purpose, because our next further logic blocks will also get delayed and as a whole the total propagation of output is delayed. All the circuits are clock or timing driven, you have to take care of timing like at every time instant it has to reach a certain voltage level and trigger a certain task,,or else there is not value of designing a fast processors and all. If this has not clarified your doubt, feel free to comment , I will respond back for sure within 24hr and please do hit that subscribe button , it will help me a lot . Thank you
@@KarthikVippala hello karthik, im really thakful for you for sharing such a good stuff and im getting stronger in basic after watching and learning from your videos. I have a small request from my side. If possible can you please share some videos on GLS , and some info on Protocols which we are using in VLSI verification like Amba protocols, Pcie protocols. It will be really helpful for us if you make some videos on that.
If you have any doubts please feel free to comment below , I WILL ANSWER YOUR DOUBTS WITHIN 24 HRS. Thanks for watching , PLEASE DO SUBSCRIBE , IT WILL HELP , ME A LOT.
Namaste Mounika _/\_, thank you so much for watching all videos , fanout load property is an element of fanout , each wire connected to driver will have a fanout load value predetermined. sum of all fanout_load gives us fanout. please excuse me , I may not be able to answer to all ur comments , thanks for asking really appreciate it. Good luck and great health.
Aravind , thank you for asking the question As fan-in increases , loading(input capacitance) will be to high for any gate to operate correctly. So in library of gates we have , maximum fan-in that a gate can support. Here library is given by fab industry. Hope this has cleared your doubt. Please do subscribe , so that we can get connected.
Hi, thanks so much for the video, it's really helpful!
I've got a question: if the we've got a logic gate with a maximum fanout 3 and also give it 3 outputs A, B, C, the input-voltage for each of those three a third of what went into the gutter, right? If so, if we repeat this (So we connect for a example b to a not-gate, that fans out into the more than one outputs and so on) would the voltage eventually become too low in one of those outputs? Bc we've split it so often. I don't really understand the difference between what I just described or just a using more outputs than the maximum fan out, which you said results in too low voltage in the outputs.
Hi Rodriguez , thank you so much for asking question.
Fan-out is measure of how much max capacitance, output can drive.
Let say , AND gate is having max fan-out of 3 (say it can drive 3 pf
capacitance) , and it is connected to three NOT gates (say A,B,C are 3
NOT gates) and so output of AND gate will drive 1 pf for each NOT gate
.
Now lets add extra NOT gate(input capacitance 1 pf) for the output of
AND gate , since max fan-out is 3 , but we are adding an extra gate
will result in slow change in output .
Voltage will not be reduced.
Slow change in voltage means : let's say at 1sec you required your voltage level to reach 1volts ,but due to slow change from the effect of extra capacitance at 1sec now the voltage will not reach 1volt ,it may reach at a later point say at 1.3seconds ,but that doesn't solve the purpose, because our next further logic blocks will also get delayed and as a whole the total propagation of output is delayed.
All the circuits are clock or timing driven, you have to take care of timing like at every time instant it has to reach a certain voltage level and trigger a certain task,,or else there is not value of designing a fast processors and all.
If this has not clarified your doubt, feel free to comment , I will respond back for sure within 24hr and please do hit that subscribe button , it will help me a lot .
Thank you
Hey , do you need video on any topic , please comment , If I know the topic ,I will make a video .
Thank you once again for asking the question.👍🙏
@@KarthikVippala thank you so much for your quick answer! Will definitely recommend your channel :)
@@fibilottarodrigez1184 thank you for your support 🙏
@@KarthikVippala hello karthik, im really thakful for you for sharing such a good stuff and im getting stronger in basic after watching and learning from your videos. I have a small request from my side. If possible can you please share some videos on GLS , and some info on Protocols which we are using in VLSI verification like Amba protocols, Pcie protocols. It will be really helpful for us if you make some videos on that.
Beautifully Explained! Thanks a lot brother, Jai Hind
Thanks bhai🙏, Jai hind
I was looking for simply, concrete and understandable graphics and concepts like this. I apreciate and thank you so much!
You have done a good job and people who are talking about accent should concentrate on the topic more than the accent..
Thanks for the support 🙏
If you have any doubts please feel free to comment below , I WILL ANSWER YOUR DOUBTS WITHIN 24 HRS.
Thanks for watching , PLEASE DO SUBSCRIBE , IT WILL HELP , ME A LOT.
Tauba Tauba Sara mood kharab kr diya is tarah ki inglish😜bol ke
😂😂😂😂
Improving on it 👍
@@KarthikVippala bhai normal accent bol bna kar bolta hai toh ajeeb lagta hai
Ok bhai
Don't listen to anyone bro,accent isn't important,the knowledge you have is important. Best of luck for your future 😉👍👍
Thanks for the support 🙏🤝
your accent is just ammazing brother. its too good 😍 👍
Thank you🙏
Mosquito 🦟 roaming near your mic huh, 😂 i got irritated,so i ran to another room but i did'nt knew that it was the audio😂
🤣
Thanks from Ethiopia. It was helpful
Namaskaram Temesgen Lemma🙏, thanks for the support, good luck & great health 👍😊
What is fanout load property and it's significance, and how we calculate?
Namaste Mounika _/\_, thank you so much for watching all videos , fanout load property is an element of fanout , each wire connected to driver will have a fanout load value predetermined. sum of all fanout_load gives us fanout.
please excuse me , I may not be able to answer to all ur comments , thanks for asking really appreciate it.
Good luck and great health.
really appreciate this! thanks
Very nice explanation...!! I just understood Fan-out more clearly...haha...! THANK U SO MUCH..^_^
Hi Raj , thanks for feedback 👍,any doubts in digital electronics and need video on other topics , pls feel free to suggest or comment 👍
@@KarthikVippala ok sir..😊 thnk u..!
Could you help me explain load cap and diffusion cap in Vlsi design attached illustration of picture, please? Thank you so much.
But why are you trying to mimic...just be you...!!
I was just trying ,this is my first time , thank you for your feedback
What happens if we degrade the output voltage level in fan-out
Thank you
what is problem in fan-in and how to solve it??
Aravind , thank you for asking the question
As fan-in increases , loading(input capacitance) will be to high for any gate to operate correctly.
So in library of gates we have , maximum fan-in that a gate can support.
Here library is given by fab industry.
Hope this has cleared your doubt.
Please do subscribe , so that we can get connected.
Sir aap Gajab ki English bol rahe hai
Thank u 🙏
Explanation is great but English is
Dangerous, simple makes more attraction then rubbbich.
Sure will improve on it
Sar aap ki Englishiss badi achiii haiii sirr
Thanks improving on it🙏
Amazing ❤👏
Thank you🙏
USEFUL
thank you :)
Pls don't use fake accent be real
This is my first time , so it has happened , thank you so much for feedback 🙏
Good work and good accent. Greetings from Mexico
Thank you Luis 😊😊, good luck good health 👍
Humble request bro try to speak in normal English don't try accent
Sure, improved in latest videos
Please drop the fake accent
Improving on it
Are you indian??
Yup 👍
@@KarthikVippala amazing bro
Thank you for the support 👍
Angrej kahe bn rahe ho bro
Namaskaram Abhishek, I have improved on it please check my latest videos, good luck & great health, Take care :)
Your English is good
Desi padhao😂