No matter how hard I try to understand it, how much research I've done so far, how many articles I've read and how many videos I've watched, my brain still can't comprehend with the fact that we, human beings, are able to create something like this just from, basically, a sand. And how in a span of 50 years we went from physical contactor switches, punch cards and tubes to quantum tunnelling and 5nm process. Just shows that the best ever cpu created was indeed a human brain.
Tbh this isnt impressive at all its just lithography Building stuff smaller is the easy part Building the actual cpu design using nothing but boolean logic to do everything on top of everything else even quantum mechanics now to make sure traces vias etc are laid correctly dont leak electrons etc is the hard part The human brain is the fastest computer ever and most efficient using only 20w
look at a motherboard then keep shrinking it. A logic gate is like an American Indian creating smoke signals, from there it went to morse code, then light and so on.
The aluminium interconnects is something that is actually still very common in the industry. One reason is that it took until the mid 90's before the industry found a way to cleanly etch copper bellow about 50 µm trace widths, and it is a more involved process, though not without its own advantages, but CMP can also be used on aluminium. Another much more prevalent reason for why aluminium is still used is that aluminium isn't toxic to semiconductors. Copper turns a transistor into a resistor as the copper diffuses into the silicon. Aluminium is a weak P dopant and forms a depletion region when in contact with another dopant. This extra depletion region can be accounted for, but beyond that the transistors still works like they should. (most good electrical conductors are actually fairly toxic to semiconductors in the same way as copper. Even tungsten is fairly bad, but at least tungsten don't do much diffusing.) Even in chips that do use copper it is seldom used beyond the top most layer and mainly there for bulk power distribution. Layers further down are often aluminium unless the chip is very power dense, since then copper can extend down to further layers. A diffusion barrier will also be required if the chip contains copper, as to stop it from diffusing into te semiconductors over time (unless one wants the chip to fail somewhat quickly (weeks/months depending on operating temperature)). But even a diffusion barrier won't stop copper from spreading, only slow it down sufficiently for a server CPU to last about 4-10 years of 24/7 operation at rated max temp before they meaningfully start failing. (depending on diffusion barrier thickness.) But a lot of modern fabs don't do copper layers at all, since copper is a risk of production contamination, so if the fab doesn't do power dense chips, then why risk it. (To my knowledge fabs that do handle copper have a division of "before copper" and "copper" sides and any wafer crossing the line won't ever return back. Same for machinery used on the copper side will never be used for anything on the before copper side (with an exception of wafer transport machinery, but perhaps even these have a strict side they stay on). Metal contamination is a serious issue in this industry. Similar to how silicone grease/oil is a serious issue for a metal paint shop) I myself is though curious to if typical DRAM chips contains copper layers or not. I wouldn't be surprised if they don't, since yield is so paramount to profit in this market where margins are honestly rather slim. Nor are RAM chips all that power dense, so not much reason for going for copper. (I will though make an exception to copper landing pads for wire bonds or flip chip, since this is somewhat typical and not uncommon to do outside of the main fab itself so that contamination is even less of an issue.)
Aluminium is widely used in bipolar power transistors - the old TO3 case. Problem with aluminium is the thermal fatigue; the commercial version of a 2N3055 is specified for 5K cycles. The MIL version uses gold to connect the transistor chip to the pins, and it can do >1M thermal cycles. As you said, copper can't be used for interconnections, it destroy the gain of the transistor in a short time...
@@rayoflight62 I can see you are talking about bond out, I however weren't. I have never heard of any manufacturer using aluminium bond wires to be fair. Gold were practically the only thing in town until copper bond wires started getting used. (at least for mass market chips.) Though, thermal fatigue tends to be a bit abnormal for any microscopic structure, like bond wires. Since the effect is due to induced stress from materials of different thermal expansion. But said stress needs to overcome the bonding strength of the two materials for the fatigue to happen and that is unlikely when the interface is only a few tenths of µm wide at most. Flip chip however suffers from thermal induced fatigue a lot faster, since the chip and its carrier cover a much larger area than a single bond wire connection. So even if the pins/balls at the edges are tiny, the difference in expansion on either side of the pin/ball will tear it apart. Meanwhile bond wires have the luxury of being able to just gradually follow along. Spreading out the stress along the length of the bond wire, and that effectively removes fatigue. Though, high G forces can knock the wire over and short it to the neighbor. Then there is plastic encapsulated packages that can trap moisture inside them. When heated during soldering the moisture can boil, and the resulting pressure can create a gas pocket between the chip and plastic, tearing off the bond wires in the process and often leaving an intermittent connection as a result. In regards to what I actually talked about in the original comment. I talked about interconnect layers on the chip itself. As an example, the last interconnect layer makes the pads used for bonding out the chips. And for these on chip interconnects, thermal fatigue is rather uncommon, and often designed away through various means. Also, can't find any information about the supposed thermal fatigue and 5k thermal cycle spec of the 2N3055. (I have seen thermal cycle specs for some MLC-Caps, but never a wire bonded transistor.) Have a manufacturer/datasheet behind that claim? The 2N3055 is a jelly bean part made by everyone and their dog after all.
The problem is that copper has a very high diffusion coefficient in Si, even at low temperatures. It is at the bottom of the wafer in no time and will ruin any junction it comes in contact with. The diffusion coefficient for Al is much lower and will need higher temperatures in order to diffuse into the Si (it is also a dopant and used for making shottky diodes). However subsequent process steps can still diffuse the Al into the Si in order to cause problems with junction spiking and render the transitors useless. Also, Si dissolves easily in Al up to a certain percentage where saturation occurs. This is especially true if very shallow diffusion regions are used (which is the case already for a long time. In order to prevent junction spiking barrier layers are used, most common TiW or TiN. For modern Al interconnect they never use pure Al, there is always some Si and Cu in the layer (Cu is to slow down electromigration).
If I recall, the mask for the 4004 was publicly released. Edit: After a brief search, the masks for the entire MCS-4 chipset were released under CC-BY-NC-SA 3.0.
This is great material, there is such a disconnect for most of us about how computers actually work. Thanks for helping turn some of the mysterious magic into solid physics and chemistry in a visual format that is easy to understand.
Beautiful work. 50 years ago this the Intel 4004 was like magic. These days we have more advanced chips in cheap disposable items. If someone was able to take a 12900k back to the 70's it would seem so advanced they would probably think you possessed alien technology.
The best way I've ever heard CPUs described in a nutshell is that they're like miniaturized cities with each street and building having a specific purpose. Thinking of them on a larger scale seems to make it easier to understand.
Federico Faggin famously laid out the 4004 by himself, transistor-by-transistor. He did the same thing for the next generation processor, and did his last layout for the original Zilog Z-80, where Faggin was the CEO. While the 4004 used enhancement mode PFET silicon gate technology, the Z-80 used depletion mode Si-gate NFET technology. Faggin developed Fairchid's silicon gate process which is why Intel recruited him for the 4004 project!
Thank you for providing the images. Much appreciated. And thanks also to the viewer who sacrificed his very fine clock to the public documentation of science and engineering history.
I was totally blind to the inside of the 4004 the first times we used and programmed it. That IC looked like a wizardry in the early '70s. Thanks for the video...
Focused ion beam is quite expensive, like 5 figures I think. I develop ICs and we sent our SerDes testchip to one of them, to cut Tx from Rx so as to see how much that reduces I/O pin capacitance. Oh, and apparently you can even create new traces with FIB.
Occasionally prepared TEM lamellae in grad school with FIB and it cost our lab $300/hr through the university, though that was very likely heavily subsidized from what it would have cost to farm it out to some outside organization.
that is strange since it is usually tax sponsored, susidised, since they are usedd for medicine discoveries and making stufff like isotopes. micro ct is probabl better in most cases bbeam line is a bit strong and is used for cases were the metal does not work with ct well
Very expensive machines, I used to run one at Motorola back in the 68040 days. It was hooked into the chip database to find the traces that were to be cut and or jumpered. The designers left traces at the top level of metalization that could be easily jumped or cut as needed to change some logic functions that were uncertain, design-wise. It used gallium ions that were accelerated to chip away at the passivation (glass) that covers the aluminum traces. There was a 'sniffer' that could tell what was in the debris , ie glass or aluminum and that would tell you to stop cutting or if you've cut through. IF you wanted a trace, it put a bit of tungsten based gas W(CO6) in the chamber where the gallium ions would hit the heavy tungsten atoms and cause them to stick to the chip, forming a conductive layer. There was also a gas that acted as an insulator that could be deposited by hitting it with the scanning beam at lower energy. One of the more interesting parts of the job of being a Chip Product Engineer :)
Fascinating! It's amazing that even at that early time so much could be fit into such a small space, and astounding how much can be fit now. It would be cool to see images and cross-sections of the results of cosmic particle strikes on microchips. No doubt this would be a much more difficult task...
@@madson-web oooooh, did you just throw the Z80 in there as well? I really like you. My memory was playing up with me, that's all (stoner). I adore both the Amiga and the Spectrum. Actually have a spare 68000 sitting here for one of my ongoing, mostly unsuccessful Amiga restorations
As I recall, PMOS was used first because it was the easiest to fabricate. Later they switched to NMOS. RCA built the first CMOS microprocessor, the COSMAC 1802.
This was amazing. Thanks for taking the (very long) time to get the results. I actually have one of those clocks and now I want to bust it open. :) Don't worry I won't.
Back then there was no CAD/CAM, so the chips like the 4004 were actually designed with rug sized drawings of the various layers, similar to architectural drawings showing the various layers of a floor design. Those drawings were then reduced to smaller and smaller transparencies to make the various layer exposure masks for the wafer chips. I think there is a photo online showing Faggin and the other designers walking on top of the design "rug" drawing. I love old chips since they are easier to see details with optical microscopes. It would be interesting to see an 8008 or 8080 for comparison.
When I used to do die failure analysis, it is possible to etch away the plastic (epoxy) packaging to reveal the die attached to the lead frame. You can do the exact same with ceramic packaging, to release the cover and the top part of the "sandwich". To release the die from the lead frame is more difficult, depending on if it was glued on or ultrasonically bonded. Acid may be needed... But for this experiment, you could have cut through the lead frame as well. Great video. Lots of memories...
Yeah interesting vid. The original discrete MOSFETs (circa 1960) used aluminum as the transistor's electrode (rather than polysilicon). It was Fairchild that first experimented with SGTs (Silicon gate technology transistors) as a variant of the metal oxide layer (they were still MOSFETs though) but used polysilicon instead of metal in the trannie's electrode for the gate-oxide layers. That was Federico Faggin that created that process for Fairchild as self-aligned gates. Interestingly, and this may provide some of that missing details you mentioned, Faggin then moved on from Fairchild and joined Intel and took the SGT concept into Intel where he immediately used it when tasked to design the 4004 chip. So the 4004 uses SGT gate technology as you correctly identified there, which relies on polysilicon/polycrystaline-silicon gates (with underlying dielectric oxide layer to produce the field-effect).
The "first" of anything always fascinates me, and the 4004 is no exception. Some NOS samples or even pulls are fetching $300-400 or more on ebay. BTW it's no surprise that MOS/CMOS devices are so static sensitive - the ultra thin SiO2 layer between the polysilicon and substrate (gate) can easily be punched through with just several hundred volts ESD and you won't even feel it. I would imagine todays nm feature sized chips are even more sensitive.
Most modern devices have internal protection diodes on the pins to reduce ESD sensitivity. Early CMOS didn’t, which is why they’re so very sensitive to ESD damage.
@@tookitogo yes true but that protection only covers to about 2000-4000 volts...better than the original tech but you can easily generate 10s of thousands of volts just raising your arm with synthetic fabric on a dry day.
@@tookitogo yes true but that protection only covers to about 2000-4000 volts...better than the original tech but you can easily generate 10s of thousands of volts just raising your arm with synthetic fabric on a dry day.
Excellent as always. Thanks for this. I posted a link where Stan Mazor will likely see it. Perhaps he'll have a useful comment or two. :) (Stan was one of the designers / implementors.)
What breaks my mind the most: That we could achieve such small constructions at that time, and yet, other tech was bad. Not bad in a sense that we were moving forward but, still, the level of differences.
Would be interesting to see a set of videos working with a fab to make a simple large transistor chip, and have chips at each layer made. That would allow a good way to look at through a basic microscope at different layers. Being a more simple chip design you could easily point out how it's working based on what pins are active at any time. Maybe even some 3D printed models to give a larger representation of different types of transistors at a scale you can easily point to and describe, or have parts you can swap to better show a change. Really going all out could have a program to show the circuit design and can show the circuit based on inputs to give a visual active view of the chip. I've always had a hard time fully grasping how these chips work at a basic level, since the basic and overly simplified graphics of some videos and articles just don't have enough there to fully follow (at least for me), and the crazy scanning electron microscope stuff is neat but goes a bit over my head. But on the other hand when I found a game on steam for making circuits and had decided to try and build the 4004 in it, I was finally able to start grasping how it worked since it was at a scale where you can more easily follow along with what's going on, as long as you could find the right info delivered in the right way (which takes a painful amount of digging even for the 4004 in my experience and for the level of info that worked best for me). Well that was a lot more than I expected to write, all just to say you do awesome videos and in the crazy chance you could, it would be neat to see something like that in collaboration with a fab that can help make that happen.
Both Intel and AMD are innovators. Specially late 90's upto abt. 2010 they both drove eachother to greater hights of technology until AMD made somehow a booboo and Intel reigned for abt 8 to 10 years and now they are driving eachother to new hights.
@@j340_official Robert Noyce, the founder of Intel, developed the monolithic integrated circuit. Like he invented chips. Someone else had made a microcircuit before Noyce but it wasn't on a single crystal of silicon like they're made today. Noyce developed the method everyone uses to make integrated circuits. He created the microelectronic industry.
10:34, is not quite correct. In a PMOS the charge carriers are holes (not electrons). But in the NMOS the charge carriers are electrons (not holes). So what this means is for the PMOS situation, holes flow from source to drain. In the NMOS electrons flow from source to drain. So in effect, the PMOS sees electrons flowing from drain to source (not from source to drain since those are the holes). Hope that makes sense. Even a lot of electronic engineers get confused on that point though!
Hmm so 125x on a modern CPU .. This 4004 CPU is ~ 2300 transistors, so ~ 48 x 48 transistors at 12mm2 square and we can see them all with a 125x magnification. A Zen 3 on TSMC N7 has 4.15B transistors in an 80.7mm2 space, or about 617M transistors in the same 12mm2, or 24839 x 24839 transistors in that same space. You'd need 500x additional magnification.. to see 1 transistor.
There is truly spectacular insight to be gathered from understanding what this technology represents for its time period if you think about your regular everyday common person in the 70s and how many of them had absolutely no clue what their government and companies were creating the Gap in understanding is astronomical not to mention the very intelligent that had no understanding of this so apply that to today and yes we have the internet we have more access to information now and I'm quite sure a lot of very intelligent people can tell me a lot of very interesting things about our technology today but let us for a second entertain the notion that same Gap still exists today what in the hell do we possess I shudder at the thought alone
These old chips show much more of the process - you see dips in the silicone - layers above of deposites... That shows more clearly how they were build... Looking at the other video, its stunning how sharp and small those traces and gates are made today... Got to love this tech :D
No matter how hard I try to understand it, how much research I've done so far, how many articles I've read and how many videos I've watched, my brain still can't comprehend with the fact that we, human beings, are able to create something like this just from, basically, a sand. And how in a span of 50 years we went from physical contactor switches, punch cards and tubes to quantum tunnelling and 5nm process. Just shows that the best ever cpu created was indeed a human brain.
Tbh this isnt impressive at all its just lithography
Building stuff smaller is the easy part
Building the actual cpu design using nothing but boolean logic to do everything on top of everything else even quantum mechanics now to make sure traces vias etc are laid correctly dont leak electrons etc is the hard part
The human brain is the fastest computer ever and most efficient using only 20w
It really makes us think that it's some kind of incredible reverse engineered Alien technology 😁😎
@@guily6669 so i guess pictures are too since they use the same tech
look at a motherboard then keep shrinking it. A logic gate is like an American Indian creating smoke signals, from there it went to morse code, then light and so on.
The best so far, except perhaps for aliens.
So nice to see the cat being so relaxed😘
Ever since Steve's cat Snowflake @ Gamers Nexus jumped up on the table during a shot one day, everyone has had a cat in their videos.
AKA static electricity source.
@@davep8221 A lovable fuzz-ball chock full of Electronic Death. Lol
The aluminium interconnects is something that is actually still very common in the industry.
One reason is that it took until the mid 90's before the industry found a way to cleanly etch copper bellow about 50 µm trace widths, and it is a more involved process, though not without its own advantages, but CMP can also be used on aluminium.
Another much more prevalent reason for why aluminium is still used is that aluminium isn't toxic to semiconductors.
Copper turns a transistor into a resistor as the copper diffuses into the silicon. Aluminium is a weak P dopant and forms a depletion region when in contact with another dopant. This extra depletion region can be accounted for, but beyond that the transistors still works like they should. (most good electrical conductors are actually fairly toxic to semiconductors in the same way as copper. Even tungsten is fairly bad, but at least tungsten don't do much diffusing.)
Even in chips that do use copper it is seldom used beyond the top most layer and mainly there for bulk power distribution. Layers further down are often aluminium unless the chip is very power dense, since then copper can extend down to further layers. A diffusion barrier will also be required if the chip contains copper, as to stop it from diffusing into te semiconductors over time (unless one wants the chip to fail somewhat quickly (weeks/months depending on operating temperature)). But even a diffusion barrier won't stop copper from spreading, only slow it down sufficiently for a server CPU to last about 4-10 years of 24/7 operation at rated max temp before they meaningfully start failing. (depending on diffusion barrier thickness.)
But a lot of modern fabs don't do copper layers at all, since copper is a risk of production contamination, so if the fab doesn't do power dense chips, then why risk it. (To my knowledge fabs that do handle copper have a division of "before copper" and "copper" sides and any wafer crossing the line won't ever return back. Same for machinery used on the copper side will never be used for anything on the before copper side (with an exception of wafer transport machinery, but perhaps even these have a strict side they stay on). Metal contamination is a serious issue in this industry. Similar to how silicone grease/oil is a serious issue for a metal paint shop)
I myself is though curious to if typical DRAM chips contains copper layers or not. I wouldn't be surprised if they don't, since yield is so paramount to profit in this market where margins are honestly rather slim. Nor are RAM chips all that power dense, so not much reason for going for copper. (I will though make an exception to copper landing pads for wire bonds or flip chip, since this is somewhat typical and not uncommon to do outside of the main fab itself so that contamination is even less of an issue.)
Aluminium is widely used in bipolar power transistors - the old TO3 case.
Problem with aluminium is the thermal fatigue; the commercial version of a 2N3055 is specified for 5K cycles. The MIL version uses gold to connect the transistor chip to the pins, and it can do >1M thermal cycles. As you said, copper can't be used for interconnections, it destroy the gain of the transistor in a short time...
@@rayoflight62 I can see you are talking about bond out, I however weren't.
I have never heard of any manufacturer using aluminium bond wires to be fair. Gold were practically the only thing in town until copper bond wires started getting used. (at least for mass market chips.)
Though, thermal fatigue tends to be a bit abnormal for any microscopic structure, like bond wires. Since the effect is due to induced stress from materials of different thermal expansion. But said stress needs to overcome the bonding strength of the two materials for the fatigue to happen and that is unlikely when the interface is only a few tenths of µm wide at most.
Flip chip however suffers from thermal induced fatigue a lot faster, since the chip and its carrier cover a much larger area than a single bond wire connection. So even if the pins/balls at the edges are tiny, the difference in expansion on either side of the pin/ball will tear it apart.
Meanwhile bond wires have the luxury of being able to just gradually follow along. Spreading out the stress along the length of the bond wire, and that effectively removes fatigue. Though, high G forces can knock the wire over and short it to the neighbor.
Then there is plastic encapsulated packages that can trap moisture inside them. When heated during soldering the moisture can boil, and the resulting pressure can create a gas pocket between the chip and plastic, tearing off the bond wires in the process and often leaving an intermittent connection as a result.
In regards to what I actually talked about in the original comment. I talked about interconnect layers on the chip itself. As an example, the last interconnect layer makes the pads used for bonding out the chips. And for these on chip interconnects, thermal fatigue is rather uncommon, and often designed away through various means.
Also, can't find any information about the supposed thermal fatigue and 5k thermal cycle spec of the 2N3055. (I have seen thermal cycle specs for some MLC-Caps, but never a wire bonded transistor.) Have a manufacturer/datasheet behind that claim? The 2N3055 is a jelly bean part made by everyone and their dog after all.
that was a great read. thanks!
This thread of comments should be Required Reading for anyone watching these videos! 😎👍☕
The problem is that copper has a very high diffusion coefficient in Si, even at low temperatures. It is at the bottom of the wafer in no time and will ruin any junction it comes in contact with. The diffusion coefficient for Al is much lower and will need higher temperatures in order to diffuse into the Si (it is also a dopant and used for making shottky diodes). However subsequent process steps can still diffuse the Al into the Si in order to cause problems with junction spiking and render the transitors useless. Also, Si dissolves easily in Al up to a certain percentage where saturation occurs. This is especially true if very shallow diffusion regions are used (which is the case already for a long time. In order to prevent junction spiking barrier layers are used, most common TiW or TiN. For modern Al interconnect they never use pure Al, there is always some Si and Cu in the layer (Cu is to slow down electromigration).
Everyone looking on cat with thoughts in my head: “I wanna pet you”.
If I recall, the mask for the 4004 was publicly released.
Edit: After a brief search, the masks for the entire MCS-4 chipset were released under CC-BY-NC-SA 3.0.
This is great material, there is such a disconnect for most of us about how computers actually work. Thanks for helping turn some of the mysterious magic into solid physics and chemistry in a visual format that is easy to understand.
Amazing work! Really interesting to see how advanced these chips already were 50 years ago, and how far we have come since then.
Beautiful work. 50 years ago this the Intel 4004 was like magic. These days we have more advanced chips in cheap disposable items. If someone was able to take a 12900k back to the 70's it would seem so advanced they would probably think you possessed alien technology.
now, many people think that crop circles are alien technology, this 1971 chip is already way more complex to make
The best way I've ever heard CPUs described in a nutshell is that they're like miniaturized cities with each street and building having a specific purpose. Thinking of them on a larger scale seems to make it easier to understand.
Tiny brains
A whole universe with tiny countries and inside tiny states with 100s of cities with 1000s of rural areas. Lol it's definitely is so astounding.
Federico Faggin famously laid out the 4004 by himself, transistor-by-transistor. He did the same thing for the next generation processor, and did his last layout for the original Zilog Z-80, where Faggin was the CEO. While the 4004 used enhancement mode PFET silicon gate technology, the Z-80 used depletion mode Si-gate NFET technology. Faggin developed Fairchid's silicon gate process which is why Intel recruited him for the 4004 project!
An Italian Masterpiece, like always. Thx Federico Faggin.
ion cannon activated
..only from Low Orbit
Well done Commander.
@@jaykay5369 pls no LOICs guys. Or HOICs xD
Thank you for providing the images. Much appreciated.
And thanks also to the viewer who sacrificed his very fine clock to the public documentation of science and engineering history.
I was totally blind to the inside of the 4004 the first times we used and programmed it. That IC looked like a wizardry in the early '70s.
Thanks for the video...
it's still amazing that they could make this in 1971
Focused ion beam is quite expensive, like 5 figures I think. I develop ICs and we sent our SerDes testchip to one of them, to cut Tx from Rx so as to see how much that reduces I/O pin capacitance. Oh, and apparently you can even create new traces with FIB.
Occasionally prepared TEM lamellae in grad school with FIB and it cost our lab $300/hr through the university, though that was very likely heavily subsidized from what it would have cost to farm it out to some outside organization.
that is strange since it is usually tax sponsored, susidised, since they are usedd for medicine discoveries and making stufff like isotopes. micro ct is probabl better in most cases bbeam line is a bit strong and is used for cases were the metal does not work with ct well
Very expensive machines, I used to run one at Motorola back in the 68040 days. It was hooked into the chip database to find the traces that were to be cut and or jumpered. The designers left traces at the top level of metalization that could be easily jumped or cut as needed to change some logic functions that were uncertain, design-wise. It used gallium ions that were accelerated to chip away at the passivation (glass) that covers the aluminum traces. There was a 'sniffer' that could tell what was in the debris , ie glass or aluminum and that would tell you to stop cutting or if you've cut through. IF you wanted a trace, it put a bit of tungsten based gas W(CO6) in the chamber where the gallium ions would hit the heavy tungsten atoms and cause them to stick to the chip, forming a conductive layer. There was also a gas that acted as an insulator that could be deposited by hitting it with the scanning beam at lower energy.
One of the more interesting parts of the job of being a Chip Product Engineer :)
6:35 you can contact Federico Faggin, he worked in this CPU and he might be happy to explain what you have in all the images :)
Just because Low Spec Gamer talked with him doesn't mean he would talk with anyone you say. :-/
Not unless you ask nicely, then maybe...
Fascinating! It's amazing that even at that early time so much could be fit into such a small space, and astounding how much can be fit now.
It would be cool to see images and cross-sections of the results of cosmic particle strikes on microchips. No doubt this would be a much more difficult task...
I can't believe we're on a working 5nm. I wonder if sub 3nm would ever be possible
This is an amazing work! I wished we could get some of these images for other classic processors such as the Motorola MC68000, Zilog z80 and MOS 6502
Count me in for interest on the 68000. That powered the A500, right? The Motorola one?
@@Kholaslittlespot1 Exactly. Ok I edited it to clarify
@@madson-web oooooh, did you just throw the Z80 in there as well? I really like you.
My memory was playing up with me, that's all (stoner). I adore both the Amiga and the Spectrum. Actually have a spare 68000 sitting here for one of my ongoing, mostly unsuccessful Amiga restorations
It always amazes me how little we know of the technology we are using daily.
Especially the red/yellow hairy cylinder on his desk.
Love this series, thank you. It wasn't too technical
Fascinating! Thanks for showing how a 50 years old CPU was assembled.
I just want to say that I appreciate you putting the ad tag in the corner. Most ads are nothing that I’m looking for.
But then I was annoyed by the UA-cam ad.
Found your channel by way of your 13900K power testing vid. Loving the vids so far!
As I recall, PMOS was used first because it was the easiest to fabricate. Later they switched to NMOS. RCA built the first CMOS microprocessor, the COSMAC 1802.
I programmed for that thing once just for fun. It's awful. And I'm glad we applied CMOS technology to much more intuitive architectures. Lol
@@EvilSandwich I do wish they had dropped the sixteen 16 bit registers to just 8 and used the extra space for a better instruction set and layout.
This was amazing. Thanks for taking the (very long) time to get the results. I actually have one of those clocks and now I want to bust it open. :) Don't worry I won't.
Back then there was no CAD/CAM, so the chips like the 4004 were actually designed with rug sized drawings of the various layers, similar to architectural drawings showing the various layers of a floor design. Those drawings were then reduced to smaller and smaller transparencies to make the various layer exposure masks for the wafer chips. I think there is a photo online showing Faggin and the other designers walking on top of the design "rug" drawing. I love old chips since they are easier to see details with optical microscopes. It would be interesting to see an 8008 or 8080 for comparison.
4:46 It is so cute to see the cat's belly move as the cat breathes! Adorable!
When I used to do die failure analysis, it is possible to etch away the plastic (epoxy) packaging to reveal the die attached to the lead frame.
You can do the exact same with ceramic packaging, to release the cover and the top part of the "sandwich".
To release the die from the lead frame is more difficult, depending on if it was glued on or ultrasonically bonded. Acid may be needed... But for this experiment, you could have cut through the lead frame as well.
Great video. Lots of memories...
It just amazes me that this is from 1971. Even then its incredible how small the circuitry is even though there are only 2300 transistors.
8:20 PCBs do have multiple layers. usually between 4 and 8, but you can make PCBs with 100 layers too.
Thanks for the semiconductor lecture.
I’m halfway through Federico Faggin’s autobiography “Silicon” right now, so this video is pretty coincidental! I actually recognize the various parts!
The effort that went into making this this video is incredible!
Wow, and this one is from over 50 years ago...That's really mind blowing.
Yeah interesting vid. The original discrete MOSFETs (circa 1960) used aluminum as the transistor's electrode (rather than polysilicon). It was Fairchild that first experimented with SGTs (Silicon gate technology transistors) as a variant of the metal oxide layer (they were still MOSFETs though) but used polysilicon instead of metal in the trannie's electrode for the gate-oxide layers. That was Federico Faggin that created that process for Fairchild as self-aligned gates. Interestingly, and this may provide some of that missing details you mentioned, Faggin then moved on from Fairchild and joined Intel and took the SGT concept into Intel where he immediately used it when tasked to design the 4004 chip. So the 4004 uses SGT gate technology as you correctly identified there, which relies on polysilicon/polycrystaline-silicon gates (with underlying dielectric oxide layer to produce the field-effect).
Thanks for adding that, very interesting
He knows he's the star of the video, and he's asserting his dominance over his human attendant. So cute.
3:25 ❤️ that scale where it was so easy to see (and the fact that it was never in a package also helped a lot)
8:06 about 1000x times more dense in each direction, from 10 micron to 10 nm is actually incredible
The "first" of anything always fascinates me, and the 4004 is no exception. Some NOS samples or even pulls are fetching $300-400 or more on ebay. BTW it's no surprise that MOS/CMOS devices are so static sensitive - the ultra thin SiO2 layer between the polysilicon and substrate (gate) can easily be punched through with just several hundred volts ESD and you won't even feel it. I would imagine todays nm feature sized chips are even more sensitive.
Most modern devices have internal protection diodes on the pins to reduce ESD sensitivity. Early CMOS didn’t, which is why they’re so very sensitive to ESD damage.
@@tookitogo yes true but that protection only covers to about 2000-4000 volts...better than the original tech but you can easily generate 10s of thousands of volts just raising your arm with synthetic fabric on a dry day.
@@tookitogo yes true but that protection only covers to about 2000-4000 volts...better than the original tech but you can easily generate 10s of thousands of volts just raising your arm with synthetic fabric on a dry day.
@@chrisguli2865 Which is why I said they *reduce,* not *eliminate,* sensitivity to ESD damage.
5:56 it has been a while
your arm became an art installation
:D
Excellent as always. Thanks for this. I posted a link where Stan Mazor will likely see it. Perhaps he'll have a useful comment or two. :) (Stan was one of the designers / implementors.)
Always interesting and unique videos from you Roman 😎
i actually enjoyed seeing your cat
We need more of this series.
This was amazing to watch. Thanks!
Really is insane how far we have come.
Wow… just impressive journey from where it’s come to now
What you do is awesome. Maybe not as awesome as the people who pioneered these devices, but still...awesome. thank you. 😁
Got a whole sleeve in 9 months. Damn tha musta been a big piece
was very distracted by the kitty that found the warm cozy spot made by the dark fabic and bight lights. lol
Respect for the cat 😊😊😊
Wow, this video is awesome. Thank you for sharing.
Ooooo, I've been really excited for this one!
Awsome Video! Great insight and Hats off for your hard work.
What breaks my mind the most: That we could achieve such small constructions at that time, and yet, other tech was bad. Not bad in a sense that we were moving forward but, still, the level of differences.
Would be interesting to see a set of videos working with a fab to make a simple large transistor chip, and have chips at each layer made. That would allow a good way to look at through a basic microscope at different layers. Being a more simple chip design you could easily point out how it's working based on what pins are active at any time. Maybe even some 3D printed models to give a larger representation of different types of transistors at a scale you can easily point to and describe, or have parts you can swap to better show a change. Really going all out could have a program to show the circuit design and can show the circuit based on inputs to give a visual active view of the chip.
I've always had a hard time fully grasping how these chips work at a basic level, since the basic and overly simplified graphics of some videos and articles just don't have enough there to fully follow (at least for me), and the crazy scanning electron microscope stuff is neat but goes a bit over my head. But on the other hand when I found a game on steam for making circuits and had decided to try and build the 4004 in it, I was finally able to start grasping how it worked since it was at a scale where you can more easily follow along with what's going on, as long as you could find the right info delivered in the right way (which takes a painful amount of digging even for the 4004 in my experience and for the level of info that worked best for me).
Well that was a lot more than I expected to write, all just to say you do awesome videos and in the crazy chance you could, it would be neat to see something like that in collaboration with a fab that can help make that happen.
Think there's a youtuber that has been trying to make his own chips at home.
"I sawed this cpu in half!"
As a nanotechnology student. Thia is my favorite type of videos
0:19 Cat failure. ;)
It's insane how we are at 2 million times density from this
Forget to mention: a salute to Federico Faggin; this was his baby...
Yes and it's worth pointing out the F. F. initials, seen in the upper right hand corner, on most photos.
After all this time, people still have their ion Intel. Speaking of huge, that cat is pretty huge.
That sweet ginger cat is adorable
I only clicked this video for the cat. It's amazing.
Can you please dissect a recently made cpu, i9 or i7, thank you
Come for the tech,, stay for the cat. :)
Uau!!!!
Você abriu o relógio da Intel 4004?!!😮
Muito legal isto!!!😃😃😃
🖤4004🖤
Gostei👍🏼
That stuff ur talking about is Classified. Manufacturers keep it to them self. All the layers n details is top secret.
This deserves a million likes.
nice cut ✂
Intel has been an innovator I hope they get back on track and launch upcoming products on time
Both Intel and AMD are innovators. Specially late 90's upto abt. 2010 they both drove eachother to greater hights of technology until AMD made somehow a booboo and Intel reigned for abt 8 to 10 years and now they are driving eachother to new hights.
@@DeeDee.Ranged true. Kudos to amd. But Intel started the x86 revolution
@@j340_official Robert Noyce, the founder of Intel, developed the monolithic integrated circuit. Like he invented chips. Someone else had made a microcircuit before Noyce but it wasn't on a single crystal of silicon like they're made today. Noyce developed the method everyone uses to make integrated circuits. He created the microelectronic industry.
10:34, is not quite correct. In a PMOS the charge carriers are holes (not electrons). But in the NMOS the charge carriers are electrons (not holes). So what this means is for the PMOS situation, holes flow from source to drain. In the NMOS electrons flow from source to drain. So in effect, the PMOS sees electrons flowing from drain to source (not from source to drain since those are the holes). Hope that makes sense. Even a lot of electronic engineers get confused on that point though!
Hmm so 125x on a modern CPU .. This 4004 CPU is ~ 2300 transistors, so ~ 48 x 48 transistors at 12mm2 square and we can see them all with a 125x magnification. A Zen 3 on TSMC N7 has 4.15B transistors in an 80.7mm2 space, or about 617M transistors in the same 12mm2, or 24839 x 24839 transistors in that same space. You'd need 500x additional magnification.. to see 1 transistor.
Let alone Apple's M1 with 16 billion transistors for a die size smaller than Ryzen's.
There is truly spectacular insight to be gathered from understanding what this technology represents for its time period if you think about your regular everyday common person in the 70s and how many of them had absolutely no clue what their government and companies were creating the Gap in understanding is astronomical not to mention the very intelligent that had no understanding of this so apply that to today and yes we have the internet we have more access to information now and I'm quite sure a lot of very intelligent people can tell me a lot of very interesting things about our technology today but let us for a second entertain the notion that same Gap still exists today what in the hell do we possess I shudder at the thought alone
These old chips show much more of the process - you see dips in the silicone - layers above of deposites... That shows more clearly how they were build...
Looking at the other video, its stunning how sharp and small those traces and gates are made today... Got to love this tech :D
My dude, you are the mvp
0:48
"Turns out that its not that easy to de-CAT one of these chips"
I liked the days where I stood some sort of chance of understanding what's going on
Absolutely amazing! Thank you so much! More of these kinds of videos, please? 🙏
Thank you for doing it in english
I was hoping you'd cut through the Cat with an Ion Beam! 🤣
If I recall correctly, that electron radiation is a similar concept to electron ionization mass spectroscopy
Ryzen in the sponsor spot of a video about Intel's grand legacy. Ain't competition great? 🙂
omg that cat ha just chillin
Here is my knowledgeable comment of infinite technical insight and comprehension: Nice tolerances, 'bro' ..
thanks for this fun video :)
0:50 For a second there I thought david was the cat
great stuff
informative and intresting
Nice kitty mousepad you got there.
I want to know how lithography work. I could not find any video to show exactly how they build and put millions of transistors in a 2-inch square.
Nice StarGate tattoo :p
13:33 that would make a very nice tartan. The der8auer Tartan?
This is what I do for work!
This surprised me the ion beam hole looks like it is so small , it couldn’t be seen on the surface with the eyes.
And he ends with "quite technical, maybe"... (MAYBE?? 😂😂🤣🤣😂😂🤣🤣🤩🤩)
5:44 Amazing that just 9 months ago you had no sleeve and now you do
Your cat is beautiful!
Very interesting
Very cool...can it be overclocked and water cooled..lol.