Simple and easy way to understand a basic clocked comparator. The building of the circuit from simple cross coupled latch is very insightful. Keep making such informative videos. Thank you :)
In the reset phase the voltage at input of inverters would be around vdd/2. This means both transistors would be on and a current will flow. There is a constant power consumption in this design for half the clock cycle. (already checdked in cadence). Can you explain what am i missing here?
I am working on a project based on double tail comparators in cadence 90 nm, but the both outputs are same even if there is a difference in inputs ,Can someone help me with this?
Simple and easy way to understand a basic clocked comparator. The building of the circuit from simple cross coupled latch is very insightful. Keep making such informative videos. Thank you :)
This is a really good explaination of clocked comparators and was very helpful.
Thank you for the nice feedback. You're welcome :)
Your kind explanation really helpful to me! Thank you very much!!
Thank you for the nice feedback.
We are glad, that we could help :)
In the reset phase the voltage at input of inverters would be around vdd/2.
This means both transistors would be on and a current will flow. There is a constant power consumption in this design for half the clock cycle. (already checdked in cadence). Can you explain what am i missing here?
Thank you. It was amazing.
Why can't we reliably flop the comparator only by changing Vin?
I am working on a project based on double tail comparators in cadence 90 nm, but the both outputs are same even if there is a difference in inputs ,Can someone help me with this?
Why are these not available as a discrete component from any manufacturer?
i dont even see the output node?