Code coverage report in verilog tutorial (ModelSim 10.6d)

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  • Опубліковано 15 вер 2024

КОМЕНТАРІ • 19

  • @atef1994itani
    @atef1994itani 5 місяців тому +1

    thank you, that was very helpful!

  • @JunaidAhmad-eu5di
    @JunaidAhmad-eu5di Рік тому

    How to merge 5 testbenches in one coverage report? U did with one i need it with 5 testbences on 1 module?

  • @nrusingagantayat1199
    @nrusingagantayat1199 Рік тому

    Please make a video to analyze the cover report and improve the coverage if necessary..

  • @xDJerome95
    @xDJerome95 6 місяців тому

    the greatest

  • @meriemaggoune1899
    @meriemaggoune1899 3 роки тому

    I have the index.html file but it looks empty. What is wrong?

    • @TominAbraham97
      @TominAbraham97  3 роки тому

      I am not sure why you are facing this problem.

  • @habibayasser310
    @habibayasser310 Рік тому

    how do I get the report name in step 8

  • @rojivdiyavrajesh5265
    @rojivdiyavrajesh5265 3 роки тому

    Sir i am facing error
    ERROR loading design
    How can I solve?

    • @TominAbraham97
      @TominAbraham97  3 роки тому

      After which step did you get this error?

    • @berolinanongdhar7513
      @berolinanongdhar7513 3 роки тому +1

      @@TominAbraham97 sir after step 8, the error is : unknown option -vopt

    • @TominAbraham97
      @TominAbraham97  3 роки тому

      @@berolinanongdhar7513 On which tool are you running the code coverage?

    • @berolinanongdhar7513
      @berolinanongdhar7513 3 роки тому +1

      @@TominAbraham97 Model Sim 10.4 student version

    • @TominAbraham97
      @TominAbraham97  3 роки тому

      @@berolinanongdhar7513 student version does not have the code coverage license hence, you are getting this error. You will have to get the full version to run code coverage.

  • @sreemukhims
    @sreemukhims 4 роки тому

    I AM FACING ERROR IN STEP -8

  • @MrVerilog
    @MrVerilog 4 роки тому

    No audio.