Writing a Verilog Testbench

[@BrianThomas]

@aldecinc So, here's the thing. Great video by the way. I've been looking all over and yours ranks up there in how you explain what Verilog even is . I love electronics. What's your advice for someone like me who's struggling to understand what you're taking about in this video. I don't know C+ but I do understand Python.

[@bigoboss-bn5mc]

he's using verilog/vhdl not C++

[@muraliguptapenugonda9257]

Very helpful , could you please tell me in which tool you are doing it?

[@lokesh.3814]

Modelsim

[@sivakumar-lb5pk]

Which software tool you used here ?

[@atif_hamza]

its Xilinx ISE , i think

[@dn2358]

@@atif_hamza no I guess it's modelsim

[@LongHoang-xl7vj]

at the end of the video he showed the software which he used in the video. its name is riviera pro simulator

[@shreyashpatel9124]

in test bench why datatype reg is used for input pins

[@bhagiallala8897]

Because in the test benchwe driven the inputs to check function ality of our program

[@vasilisnikitaras]

Amazing!

[@bakeronews1]

How you got to the test bench???????????? Stop skipping steps!!!!!!