[Eng Sub] TIM (Thermal Interface Material)

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  • Опубліковано 14 лис 2024

КОМЕНТАРІ • 14

  • @김진호-k4c6d
    @김진호-k4c6d 4 місяці тому +1

    This is a great video for better understanding of TIM.

  • @andreashandschutz1677
    @andreashandschutz1677 5 місяців тому +1

    Thanks for that really god explanation. In terms of of receiving a better heat transfer, are there any thoughts of using Clad Material for meta lid?

    • @semicontalk3223
      @semicontalk3223  5 місяців тому

      I am not sure what kind of clad material you mean. Vapor chamber technology is used in smartphone for better heat dissipation.
      www.gizchina.com/2024/01/24/samsung-galaxy-s24-ultra-teardown/
      www.global.dnp/biz/solution/products/detail/10161128_4130.html

  • @TheBrightLi
    @TheBrightLi 2 роки тому +1

    Thank you for the great talk. Would you share any insights on hypotheses that could lead to TIM thermal run away?

    • @semicontalk3223
      @semicontalk3223  2 роки тому

      Sorry for late response. Actually I didn't understand your question so did some research to understand. Unfortunately I don't have insight on TIM thermal run away because I don't have experience for that in semiconductor packaging.

  • @owenchang2581
    @owenchang2581 Рік тому +1

    In recent years, I always see TIM for die and heat sink attachment directly. I know this should be more efficient. But there should be somehow for some applications still needs TIM2. Do you know why?

    • @semicontalk3223
      @semicontalk3223  Рік тому +1

      I don't know the reason. I tried to find related paper or information but couldn't find.
      TIM1 is used between flipchip die backside and metal lid. TIM1.5 is used between flipchip die backside and heat sink. TIM2 is used between metal lid and heat sink so TIM2 is used in addition to TIM1 with metal lid.
      The case using TIM2 means it also uses metal lid with TIM1 and I guess this metal lid is to reduce package warpage. Maybe this case, heat sink can not be attached on die backside directly which is more efficient due to high package warpage. Again, this is my guess.

    • @owenchang2581
      @owenchang2581 Рік тому +1

      Thanks for reply and agree your warpage concern. I also think maybe the die size is too small if the die produce too much heat. So applying a additional material to have better heat distribution and being a buffer if the heat cannot be conducted quickly. Just maybe.

  • @mishalmalik6439
    @mishalmalik6439 8 місяців тому +2

    Best explaination

  • @viswanathb11
    @viswanathb11 2 роки тому +2

    can you please explain about todays micro bump current carrying capability

    • @semicontalk3223
      @semicontalk3223  2 роки тому

      I am afraid that I don't have that information.

  • @TrentTYY
    @TrentTYY 3 роки тому +2

    Can you do a video on advanced / wafer level packaging?

  • @amgelectronics2769
    @amgelectronics2769 Рік тому +1

    learn it