Adventures in SIMD-Thinking (part 1 of 2) - Bob Steagall - CppCon 2020

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SIMD capabilities are virtually ubiquitous in modern computing hardware, and yet much of that computing capacity often goes unused. This talk will provide a high-level overview of the SSE, AVX, and AVX-512 instruction set architecture provided by Intel microprocessors, and provide some specific examples of real-world problems where additional performance can be gained by thinking "vertically".
We'll begin with a quick, high-level description of the features provided by the SSE, AVX, and AVX-512 instruction sets. We'll then use C++ to compose a simple API employing various compiler intrinsics implementing those instruction sets. At the lowest level, the API will wrap some primitive operations, and then build some very useful basic operations (like multi-register shift) upon those primitives. We'll then build some facilities for comparison and arithmetic, and finally round out the API with functions for load and store. During all of this, we'll use C++ to provide type safety, reduce complexity, and maximize performance.
Next, we'll take a look at how this simple API can be used to improve performance for a handful of interesting problems, like sorting the values stored in a register to create a very fast 1-D median filter, or high-speed convolution and correlation with kernels that fit within a single register. Finally, we'll revisit the UTF-8 to UTF-32 conversion techniques presented at CppCon two years ago to see whether using AVX can make an already fast conversion algorithm even faster.
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Bob Steagall
KEWB Computing
Chief Cook and Bottle Washer
Maryland
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Streamed & Edited by Digital Medium Ltd - events.digital-medium.co.uk
[e-mail]
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[@morthim]

this one talk was more valuable than all other programing stuff i've seen this year, combined.
going to rewatch it later.
but thank you. wow

[@dexterman6361]

This talk is GOLD! Love it. Amazing technical info there!

[@morwar_]

Part two: ua-cam.com/video/qXleSwCCEvY/v-deo.html&ab_channel=CppCon

[@tikabass]

In the smedian of 7, you can save a load from memory by loading 8 samples, and mm_shuffle the sort register accordingly. Your first lane of 7 stating at samples[0] and second lane of 7 starting at samples[1] make 8 samples. That would save a couple more cycles per sample. :)

[@userrand4900]

The loal_value function in slide 4 does not use the fill? Where is the register name specified?

[@taw3e8]

You used the same seed each time? Was it a compile time known value? Could compiler just do (at least some part of) the work before the code even run?

[@arkadiymel5987]

14:02 I guess alignr with the value to rotate as both vector arguments can be used instead

[@berksteraydo9517]

The new generation, gets lamer, with a passion for high-level pl's, they are just missing out. Believe me, I am new gen. Discussions of really interesting topics in cppcon. These people are so helpful.