The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. The advantage of RISC-V is open architecture. RISC-V has instructions of variable lengths. This is bad, it is a departure from the RISC architecture principles. The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems. The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems. A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not perspective for computer industry. In fact, RISC-V hampers the further development of the novel microprocessor technologies. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture: V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf): www.emodel.org.ua/en/ touch ARCHIVE, then move to 2019, then to VOL 41, NO 6(2019) pp. 77-90. This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi (V.K.Dobrovolskyi).
Really, the ideas RISC-V is based on are 60 years old, with the CDC6600 sharing all the important characteristics of modern RISC. The principles of starting from simplicity and adding only that which is proven to be beneficial were rediscovered later and have stood the test of time through many generations of computer hardware and circuit technology. Regarding variable-length instructions, this has proven to be beneficial in moderation. Having two lengths adds very little complexity even to very wide instruction decode/dispatch, but has proven to have large benefits. Certainly, having a dozen or more lengths is not helpful, but the main desirable property is being able to determine the length as quickly and easily as possible. ARM introduced two instructions lengths with Thumb2, and this resulted in their period of massive growth. Reverting to a single instruction length with Aarch64 is very like a bad idea. CDC6600 had two instruction lengths (15 and 30 bits). So did Cray 1. So did IBM's 801 research project. So did RISC I at Berkeley. RISC ISAs introduced between 1985 and 1990 has fixed instruction length, but having two lengths has been common both before and after that. It may have escaped your attention, but "powerful and advanced" firms are getting involved with RISC-V recently. The first results of this will start to appear in the market in around 2025-2026, with RISC-V chips with performance equal to today's x86 and Apple M1/M2. Of course those companies will have moved on further by then, but still I think you will find RISC-V continues to catch up and parity will probably be achieved by 2030. That is very soon. "We always overestimate the change that will occur in the next two years and underestimate the change that will occur in the next ten." Bill Gates wrote this in his 1995 book, but the same idea can be found from A C Clarke and others in the past.
Your comment sounds informed, but clearly isn't. You talk of a victory but fail to disclose what that means to you. The RV ISA supports a future containing VLIW but doesn't define any within the current or proposed specifications, unlike some of the ISAs you cite. All RV instructions are 32bit, there is support for 16bit compressed instructions which are simply aliases to a subset of the 32bit ones. These can also be mixed and interleaved with 32bit instructions, unlike some of the other ISAs you cite that need an instruction to switch between decoder modes. While you continue to persist in your comment in thinking about high performance (as if that is some unwritten concensus of the only design goal) you miss the much larger market of the 8bit and 16bit microcontroller, coprocessor and ML/AI/SDR/vector processor segment that exists in the world today. Yes there are a few high profile companies that are pushing the high performance general purpose CPU segment such as SiFive and MIPS, and yes achieving that high performance will require access to protected IP. Luckily that is available in the world today and is for sale. Luckly most users of RV will be willing to spend dollars on a hardware implementation in a physical chip form, so there is money to be made even though the base platform ISA is freely available and extendable. Now it won't take another 40y to catch up, the gap between the leading RV implementation and the leading general purpose CPU will reduce faster each year, faster than new advancement will improve those leading designs. So the question to ask in 15y is which ISA is able to achieve the most work for the least power, heat, square mm and able to achieve hardened designs easier and most cost effectively. Thanks for your book plug, but as your comment here seems uninformed I doubt it will be a useful resource to anyone looking towards to the future of CPU design. RISC-V is to CPU ISA as Linux is to operating systems. It works from a very small base and is possible to scale to the high performance segments you talk of. You expect this to be happening already in your impatience, when Linux and the ISAs you cite took decades, and regardless of your personal opinion on RV, the world will inevitably move on without you and your opinions. Just to plug who I am, I helped create Linux back in the mid/late 90s, I am credited in the top of source files because it was the pre-git era.
Dear Bruce, I thank you for your detailed and excellent analysis.
Dear D M, thank you, your analysis is very detailed and interesting, I will study it.
The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. The advantage of RISC-V is open architecture. RISC-V has instructions of variable lengths. This is bad, it is a departure from the RISC architecture principles.
The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems.
The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems.
A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not perspective for computer industry. In fact, RISC-V hampers the further development of the novel microprocessor technologies. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture:
V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf):
www.emodel.org.ua/en/ touch ARCHIVE, then move to 2019, then to VOL 41, NO 6(2019) pp. 77-90.
This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi (V.K.Dobrovolskyi).
Really, the ideas RISC-V is based on are 60 years old, with the CDC6600 sharing all the important characteristics of modern RISC. The principles of starting from simplicity and adding only that which is proven to be beneficial were rediscovered later and have stood the test of time through many generations of computer hardware and circuit technology. Regarding variable-length instructions, this has proven to be beneficial in moderation. Having two lengths adds very little complexity even to very wide instruction decode/dispatch, but has proven to have large benefits. Certainly, having a dozen or more lengths is not helpful, but the main desirable property is being able to determine the length as quickly and easily as possible. ARM introduced two instructions lengths with Thumb2, and this resulted in their period of massive growth. Reverting to a single instruction length with Aarch64 is very like a bad idea. CDC6600 had two instruction lengths (15 and 30 bits). So did Cray 1. So did IBM's 801 research project. So did RISC I at Berkeley. RISC ISAs introduced between 1985 and 1990 has fixed instruction length, but having two lengths has been common both before and after that.
It may have escaped your attention, but "powerful and advanced" firms are getting involved with RISC-V recently. The first results of this will start to appear in the market in around 2025-2026, with RISC-V chips with performance equal to today's x86 and Apple M1/M2. Of course those companies will have moved on further by then, but still I think you will find RISC-V continues to catch up and parity will probably be achieved by 2030. That is very soon.
"We always overestimate the change that will occur in the next two years and underestimate the change that will occur in the next ten." Bill Gates wrote this in his 1995 book, but the same idea can be found from A C Clarke and others in the past.
Your comment sounds informed, but clearly isn't.
You talk of a victory but fail to disclose what that means to you.
The RV ISA supports a future containing VLIW but doesn't define any within the current or proposed specifications, unlike some of the ISAs you cite. All RV instructions are 32bit, there is support for 16bit compressed instructions which are simply aliases to a subset of the 32bit ones. These can also be mixed and interleaved with 32bit instructions, unlike some of the other ISAs you cite that need an instruction to switch between decoder modes.
While you continue to persist in your comment in thinking about high performance (as if that is some unwritten concensus of the only design goal) you miss the much larger market of the 8bit and 16bit microcontroller, coprocessor and ML/AI/SDR/vector processor segment that exists in the world today.
Yes there are a few high profile companies that are pushing the high performance general purpose CPU segment such as SiFive and MIPS, and yes achieving that high performance will require access to protected IP. Luckily that is available in the world today and is for sale. Luckly most users of RV will be willing to spend dollars on a hardware implementation in a physical chip form, so there is money to be made even though the base platform ISA is freely available and extendable.
Now it won't take another 40y to catch up, the gap between the leading RV implementation and the leading general purpose CPU will reduce faster each year, faster than new advancement will improve those leading designs.
So the question to ask in 15y is which ISA is able to achieve the most work for the least power, heat, square mm and able to achieve hardened designs easier and most cost effectively.
Thanks for your book plug, but as your comment here seems uninformed I doubt it will be a useful resource to anyone looking towards to the future of CPU design.
RISC-V is to CPU ISA as Linux is to operating systems. It works from a very small base and is possible to scale to the high performance segments you talk of. You expect this to be happening already in your impatience, when Linux and the ISAs you cite took decades, and regardless of your personal opinion on RV, the world will inevitably move on without you and your opinions.
Just to plug who I am, I helped create Linux back in the mid/late 90s, I am credited in the top of source files because it was the pre-git era.
You have too much fucking time on your hands bud.