At 7:46 IN metal side Fermi level is above semiconductor Fermi level but by applying positive voltage at gate, Fermi level of metal should go down as you said in previous videos
I have a module in semiconductor devices and physics in my degree and I have never really found much interest in it due to a lack of intuition and comprehensive explanation (not for lack of trying on part of the lecturer). These videos have really sparked my interest in the topic and I'm finding myself thinking about it more and more. I very much appreciate the videos. Thank you
Hi Jordan,I am confused by the change of the band diagram. When you apply a voltage on the metal, you lower the Ef of the semiconductor band, and later when you apply further voltage, the Ef stays and other energy levels starts to bend? How should I know when to bend the energy level and when to simply lower the Ef? Thanks in advance.
Sir，Thank you for your video. And I have a question that could I regard that when the p-type changes to the n-type by applying enough gate voltage, the depletion mode is called the Inversion mode?
That’s a great question, there are a ton of electrons in whatever metal youattach to the gate, and those electrons that were in the metal will move to the interface. Whatever voltage source you have is providing the energy (in the form of electric fields) to actually do this.
@@JordanEdmundsEECS That way, threshold voltage of MOS should be equal to only the work function of metal...but that's not the case I believe. I read somewhere that at a huge voltage, electron hole pair generation takes place in bulk, the thermal generation. Please clarify this....I'm worried. Appreciate your effort in these great lectures.
Hi sir, on applying positive voltage on gate, from where the free electrons are forming the inversion region, considering its a p type SC. Is it due to domination of EHP generation, and holes being pulled down ?
Exactly, you have a certain baseline thermal electron-hole pair generation in a semiconductor regardless of the doping. In a p-type semiconductor, usually all the electrons immediately recombine with holes, but in this case we are separating them before they can recombine, and keeping them safe in the inversion region.
They are two names for the same thing. MOS literally stands for metal-oxide semiconductor, but is typically used loosely to refer to any metal-insulator-semiconductor structure. MIS (metal-insulator-semiconductor) is the “more correct” version when your insulator isn’t oxide (SiO2), but typically people are lazy and use the two interchangeably.
At 7:46 IN metal side Fermi level is above semiconductor Fermi level but by applying positive voltage at gate, Fermi level of metal should go down as you said in previous videos
Ah! Correct you are. As written it is incorrect, the Fermi energy should indeed decrease (all the bands get pushed down).
I think so energy difference is important rather than absolute energy..
I have a module in semiconductor devices and physics in my degree and I have never really found much interest in it due to a lack of intuition and comprehensive explanation (not for lack of trying on part of the lecturer). These videos have really sparked my interest in the topic and I'm finding myself thinking about it more and more. I very much appreciate the videos. Thank you
Your videos are like a live saver. Thank you. Please don't stop lecturing more.
I have an exam coming up and these video are literally saving my life!!
Aw thanks :D I’m glad they helped, good luck on your exam!
this is the best explanation video i have found on this topic
Can you share link of the video in which the calculation of threshold voltage is given?
Hi Jordan,I am confused by the change of the band diagram. When you apply a voltage on the metal, you lower the Ef of the semiconductor band, and later when you apply further voltage, the Ef stays and other energy levels starts to bend? How should I know when to bend the energy level and when to simply lower the Ef?
Thanks in advance.
what to book do you suggest for undergraduate studying (Electronics Engineering) ?
Thank you very much, you are life saver, so much hearts ♥️
Hi, Thank you so much.
I don't understand Why Vg is pointing upwards.. If it push electrons upwards, shouldn't Vg point downwards?
Hi
i have a question .....why cant imobile ions came to form electric field instead of free electrons ??
Sir，Thank you for your video. And I have a question that could I regard that when the p-type changes to the n-type by applying enough gate voltage, the depletion mode is called the Inversion mode?
I can't understand from where electron comes when we increase voltage at gate?
That’s a great question, there are a ton of electrons in whatever metal youattach to the gate, and those electrons that were in the metal will move to the interface. Whatever voltage source you have is providing the energy (in the form of electric fields) to actually do this.
@@JordanEdmundsEECS That way, threshold voltage of MOS should be equal to only the work function of metal...but that's not the case I believe. I read somewhere that at a huge voltage, electron hole pair generation takes place in bulk, the thermal generation. Please clarify this....I'm worried. Appreciate your effort in these great lectures.
good morning sir...thank you
Hi sir, on applying positive voltage on gate, from where the free electrons are forming the inversion region, considering its a p type SC. Is it due to domination of EHP generation, and holes being pulled down ?
Exactly, you have a certain baseline thermal electron-hole pair generation in a semiconductor regardless of the doping. In a p-type semiconductor, usually all the electrons immediately recombine with holes, but in this case we are separating them before they can recombine, and keeping them safe in the inversion region.
NYC presentation
Very much understanding
Thank you for this great tutorial. I like your brain.
Again a nice video Sir. After a long time. What are you majoring in Sir?
Thanks :D I'm a Ph.D. student in Electrical Engineering (Integrated Circuit Design) at Berkeley.
What is the difference between mis and mos diode and why?
Sir please reply I'm confused in that topic.
They are two names for the same thing. MOS literally stands for metal-oxide semiconductor, but is typically used loosely to refer to any metal-insulator-semiconductor structure. MIS (metal-insulator-semiconductor) is the “more correct” version when your insulator isn’t oxide (SiO2), but typically people are lazy and use the two interchangeably.
TQ sir
great work
Thanks :)
Can you please send a written version of these video.
Actually, the explaination in [Streetman - Solid State Electronic Devices 7th] is more easy to understand where he assumed фms is zero
Solve for strong inversion
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