CombCkt - 8 - Logical Effort

[@davideallegra8827]

In the end, is it g= 5/3 also for the 20x NAND ? Why is 80C instead of 100C ?

[@davideallegra8827]

Answered myself: there are 2 INs, not 3. So is 80C :-)

[@socialogic9777]

@11:16, what does it mean - "NOR will have lesser drive strength in the resistance"

[@prakashkumar833]

Nor is producing (5/4)R as penalty to match the input gate capacitance of Nand. So, the delay as penalty is 20 percent more, this is happening due to increment in R causing lesser driving capability to load. Or we can also say that lower resistance will have more driving capability, since it draw more current from source for load. Here, for Nor the driving capability is lesser in Resistance.

[@anushakuruba7111]

@@prakashkumar833 The pull up resistance of NOR is 2R/k+2R/k=4R/k,
where k=4/5. Hence, it becomes 5R. So the delay of nor is 5RC. How come it is 5/4RC

[@manoj3197]

@@anushakuruba7111 yeah even I have the same doubt if you got the answer please reply

[@sreekantasai1675]

less drive strength in the resistance means less current from Vdd to load through resistance but it doesn't mean less resistance. Here resistance will be 5R/4 and delay is 5/4(RC), Because here alpha means scaling to existing configuration but not size directly. Initially PUR is (R/2 + R/2) as width of each pmos is 4. Now it is scaled with alpha(K). So now PUR is (R/2K + R/2K) where K= 4/5. So PUR is R/K = 5R/4 and so the delay 5RC/4.

[@akashekhar]

@@manoj3197 The pull-up resistance of NOR is R/2k + R/2k = R/k, hence put k=4/5, we get 5RC/4.