Sure. What do you need help with? Simply, the stepper is there to synchronize the steps of the processor. You get one "step" signal every clock cycle that you can use with other signals and logic gates to make things happen for each step. If this doesn't help, ask some questions and I will be happy to answer them for you.
@@dajoma36 Thank you very much. This is what I have gotten so far about the stepper. Please correct or add information if possible. Each clock cycle = 1 step. The first memory bit is connected to a part that is always on in the computer. Since the memory bits are all connected in a string, that on state is present across the string. Each step turns off when this on bit goes through a NOT gate. I haven't fully understood the reset part.
@@amandaahona6562 I am thinking that you are referring to the logic schematic of the stepper? Honestly, I never really paid much attention to the schematic. I just understood what it is supposed to do and used Verilog to describe its functionality. But, if you would like to understand the schematic, please email me and I will email you back with the information from the book. Because, yeah, this is a complicated schematic and there is a lot of explaining about what goes on every clock cycle, and the reset.
Nice that u were back! Cool!
Thanks! It's great to be back.
I still have a problem understanding the stepper. Please help.
Sure. What do you need help with? Simply, the stepper is there to synchronize the steps of the processor. You get one "step" signal every clock cycle that you can use with other signals and logic gates to make things happen for each step. If this doesn't help, ask some questions and I will be happy to answer them for you.
@@dajoma36 Thank you very much. This is what I have gotten so far about the stepper. Please correct or add information if possible. Each clock cycle = 1 step. The first memory bit is connected to a part that is always on in the computer. Since the memory bits are all connected in a string, that on state is present across the string. Each step turns off when this on bit goes through a NOT gate. I haven't fully understood the reset part.
@@amandaahona6562 I am thinking that you are referring to the logic schematic of the stepper? Honestly, I never really paid much attention to the schematic. I just understood what it is supposed to do and used Verilog to describe its functionality. But, if you would like to understand the schematic, please email me and I will email you back with the information from the book. Because, yeah, this is a complicated schematic and there is a lot of explaining about what goes on every clock cycle, and the reset.
@@dajoma36 Thank you. Where can I find your email?
@@amandaahona6562 You're welcome. You can find my email on the ABOUT page of this channel. But, here it is:
d.marion8@my.denver.coloradotech.edu