FPGA Discovery (Learning How to Work with FPGAs)
FPGA Discovery (Learning How to Work with FPGAs)
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CPU Series 1: The 7-Step Processor Part 6 - CPU Verification and Programming
In this video, the functionality and correctness of design of the CPU is verified through a testing process that includes writing programs for the CPU, assembling CPU programs into binary machine codes, creating a Verilog ROM containing the machine codes, transferring machine codes to CPU memory, and driving the CPU to execute the coded instructions.
Special thanks to Wenton Davis for supporting this project by writing the assembler.
Video Corrections:
3:55 - Not "semicolon", but "colon", to mark a label in an assembly program. The semicolon in an assembly program is used for comments.
11:48 - Double click on the "Python program file", not the "ROM".
18:12 - Not back to "step 6", but back to "step 1".
24:56 - "600ns", not "60ns".
All files used in this project can be found here:
github.com/FPGADude/Digital-Design/tree/main/Microprocessor%20CPU%20Series/7%20Step%20Processor
Переглядів: 643

Відео

CPU Series 1: The 7-Step Processor Part 5 - A Complete CPU22:59CPU Series 1: The 7-Step Processor Part 5 - A Complete CPU
CPU Series 1: The 7-Step Processor Part 5 - A Complete CPU
Переглядів 324Рік тому
In this video, a new data bus design is introduced, the remaining small CPU components are created along with a couple new components. Each component is simulated to verify functionality. Finally, the complete CPU is created in one Verilog module and a preview of Part 6 discusses a plan for verifying the operation of the completed CPU. Github space containing CPU_B: github.com/FPGADude/Digital-...
Improved Nexys A7 I2C Temperature Sensor5:55Improved Nexys A7 I2C Temperature Sensor
Improved Nexys A7 I2C Temperature Sensor
Переглядів 1,4 тис.Рік тому
An improved version of the previous Nexys A7 Temperature Sensor project. Improvements: reset removed (not needed), single always block in i2c master, and added Fahrenheit temperature conversion circuitry and display capabilities. Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Improved I2C Nexys A7 Temperature Sensor
I2C on FPGA Temperature Sensor Basys3 with PmodTMP26:59I2C on FPGA Temperature Sensor Basys3 with PmodTMP2
I2C on FPGA Temperature Sensor Basys3 with PmodTMP2
Переглядів 3,6 тис.Рік тому
Using the PmodTMP2 requires modeling the PMOD pins on the FPGA with pullup resistors. The same files from Nexys A7 can then be used with PmodTMP2. This project adds functionality to switch between outputting Celsius and Fahrenheit temperature data. Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Basys3_PmodTMP2_Temp_Sensor
CPU Series 1: The 7-Step Processor Part 4 - Control Unit and Instruction Set1:03:34CPU Series 1: The 7-Step Processor Part 4 - Control Unit and Instruction Set
CPU Series 1: The 7-Step Processor Part 4 - Control Unit and Instruction Set
Переглядів 389Рік тому
This video covers the control unit schematic and the processor instruction set. This is a long video, but the information within is paramount to understanding how the processor works and how it can be utilized within a computer system. Icarus Verilog download: bleyer.org/icarus/ Project files GitHub repository location: github.com/FPGADude/Digital-Design/tree/main/Microprocessor CPU Series/7 St...
CPU Series 1: The 7-Step Processor Part 3 - Clocks and Stepper9:00CPU Series 1: The 7-Step Processor Part 3 - Clocks and Stepper
CPU Series 1: The 7-Step Processor Part 3 - Clocks and Stepper
Переглядів 375Рік тому
In this part we begin to examine the control unit in which the clock generation and stepper modules reside. We build the clock generation and stepper unit, and then test both using a Verilog test bench using Icarus Verilog and GTKWave. At the end of the video is a preview of the control unit that will be built using Verilog in Part 4. Link to Icarus Verilog and GTKWave: bleyer.org/icarus/ Link ...
CPU Series 1: The 7-Step Processor Part 2 - Arithmetic and Logic Unit (ALU)16:15CPU Series 1: The 7-Step Processor Part 2 - Arithmetic and Logic Unit (ALU)
CPU Series 1: The 7-Step Processor Part 2 - Arithmetic and Logic Unit (ALU)
Переглядів 297Рік тому
Part 2 of the 7 Step Processor series. In this video we build the ALU from the logic schematic provided in the book. Then test it using a test bench module to verify its operation. Video corrections: 12:37 - operand B is "hex 55" not "hex CC" Link to Icarus Verilog and GTKWave: bleyer.org/icarus/ Link to Github repo with project files: github.com/FPGADude/Digital-D...
CPU Series 1: The 7-Step Processor Part 1 - Main Memory (RAM)19:55CPU Series 1: The 7-Step Processor Part 1 - Main Memory (RAM)
CPU Series 1: The 7-Step Processor Part 1 - Main Memory (RAM)
Переглядів 746Рік тому
The first video in a series where we will build a simple microprocessor described in the book "But How Do It Know" by J. Clark Scott. Disclaimer: I do not personally know the author of the book, nor am I promoting this book. It is just a really cool book filled with logic schematics describing a simple 7-step microprocessor that I thought would be fun to build and test using Verilog. Video corr...
UART in Verilog on Basys3 FPGA using PuTTY15:24UART in Verilog on Basys3 FPGA using PuTTY
UART in Verilog on Basys3 FPGA using PuTTY
Переглядів 9 тис.2 роки тому
Using a UART core coded in Verilog and PuTTY terminal emulator to communicate ASCII values between a PC and an FPGA. Download PuTTY here: putty.org Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/UART
FIFO in Verilog on Basys3 FPGA14:54FIFO in Verilog on Basys3 FPGA
FIFO in Verilog on Basys3 FPGA
Переглядів 1,7 тис.2 роки тому
Creating a 3-bit data, 4-address memory FIFO in Verilog and demonstrating functionality on the Basys 3 FPGA using Vivado. Project code can be found here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/FIFO
SPI on FPGA 3-Axis Accelerometer Nexys A7 or Basys 3 w/ PmodACL2 Verilog32:29SPI on FPGA 3-Axis Accelerometer Nexys A7 or Basys 3 w/ PmodACL2 Verilog
SPI on FPGA 3-Axis Accelerometer Nexys A7 or Basys 3 w/ PmodACL2 Verilog
Переглядів 4,6 тис.2 роки тому
Reading the 3-axis accelerometer ADXL362 on the Nexys A7 using SPI serial communications protocol in Verilog using Vivado. You can also use the Basys 3 FPGA with Pmod ACL2 which has the ADXL362. Website for Icarus Verilog: iverilog.icarus.com/ Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Nexys A7 3-Axis Accelerometer SPI
I2C on FPGA Temperature Sensor Nexys A7 or Basys 3 w/ Pmod TMP2 Verilog41:27I2C on FPGA Temperature Sensor Nexys A7 or Basys 3 w/ Pmod TMP2 Verilog
I2C on FPGA Temperature Sensor Nexys A7 or Basys 3 w/ Pmod TMP2 Verilog
Переглядів 12 тис.2 роки тому
Reading the temperature sensor ADT7420 on the Nexys A7 FPGA with I2C master created using Verilog and implemented on FPGA with Xilinx Vivado. Can also use the Basys 3 FPGA with Pmod TMP2 which has the ADT7420. Website for Icarus Verilog: bleyer.org/icarus/ Project files on Github here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/NexysA7_Temp_Sensor_I2C
Counters in Logisim2:38Counters in Logisim
Counters in Logisim
Переглядів 4932 роки тому
Demonstrating four different 4-bit counters in Logisim Evolution. Binary Counter Johnson Counter LFSR, xnor version LFSR, xor version
Linear Feedback Shift Register LFSR in Verilog on Basys 3 FPGA5:25Linear Feedback Shift Register LFSR in Verilog on Basys 3 FPGA
Linear Feedback Shift Register LFSR in Verilog on Basys 3 FPGA
Переглядів 1,1 тис.2 роки тому
Demonstrating a 4-bit LFSR on Basys 3 FPGA coded in Verilog. Project files can be found here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/LFSR 4-bit
Johnson Counter in Verilog on Basys 3 FPGA4:34Johnson Counter in Verilog on Basys 3 FPGA
Johnson Counter in Verilog on Basys 3 FPGA
Переглядів 4322 роки тому
Demonstrating a Johnson Counter on the Basys 3 FPGA using Verilog. Program files can be found here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Johnson Counter 4-bit
Fibonacci Sequence Generator Circuit in Logisim Evolution4:02Fibonacci Sequence Generator Circuit in Logisim Evolution
Fibonacci Sequence Generator Circuit in Logisim Evolution
Переглядів 1,5 тис.2 роки тому
Fibonacci Sequence Generator Circuit in Logisim Evolution
Star Wars Imperial March Song on Basys 3 Verilog Vivado10:32Star Wars Imperial March Song on Basys 3 Verilog Vivado
Star Wars Imperial March Song on Basys 3 Verilog Vivado
Переглядів 1,3 тис.2 роки тому
Star Wars Imperial March Song on Basys 3 Verilog Vivado
PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado12:16PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado
PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado
Переглядів 2922 роки тому
PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado
Intro to PicoBlaze Microcontroller on Basys 3 FPGA9:55Intro to PicoBlaze Microcontroller on Basys 3 FPGA
Intro to PicoBlaze Microcontroller on Basys 3 FPGA
Переглядів 1,2 тис.2 роки тому
Intro to PicoBlaze Microcontroller on Basys 3 FPGA
Simple Register File in Verilog Simulated in Vivado6:39Simple Register File in Verilog Simulated in Vivado
Simple Register File in Verilog Simulated in Vivado
Переглядів 1,6 тис.2 роки тому
Simple Register File in Verilog Simulated in Vivado
Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado10:52Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado
Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado
Переглядів 7842 роки тому
Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado
VGA Clock & Calendar Verilog Basys 3 FPGA18:23VGA Clock & Calendar Verilog Basys 3 FPGA
VGA Clock & Calendar Verilog Basys 3 FPGA
Переглядів 1,7 тис.2 роки тому
VGA Clock & Calendar Verilog Basys 3 FPGA
A Simple ALU in Verilog Simulated in Vivado7:50A Simple ALU in Verilog Simulated in Vivado
A Simple ALU in Verilog Simulated in Vivado
Переглядів 1,9 тис.2 роки тому
A Simple ALU in Verilog Simulated in Vivado
Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado3:42Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado
Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado
Переглядів 5202 роки тому
Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado
VGA Digital Clock in Verilog on Basys 3 FPGA Vivado17:07VGA Digital Clock in Verilog on Basys 3 FPGA Vivado
VGA Digital Clock in Verilog on Basys 3 FPGA Vivado
Переглядів 3,5 тис.2 роки тому
VGA Digital Clock in Verilog on Basys 3 FPGA Vivado
VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado4:30VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado
VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado
Переглядів 1,7 тис.2 роки тому
VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado
VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado20:27VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado
VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado
Переглядів 6 тис.2 роки тому
VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado
VGA PmodENC Project Verilog Basys 3 FPGA Vivado7:04VGA PmodENC Project Verilog Basys 3 FPGA Vivado
VGA PmodENC Project Verilog Basys 3 FPGA Vivado
Переглядів 6452 роки тому
VGA PmodENC Project Verilog Basys 3 FPGA Vivado
How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado6:44How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado
How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado
Переглядів 1 тис.2 роки тому
How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado
Making the Basys 3 FPGA Portable Verilog Vivado3:37Making the Basys 3 FPGA Portable Verilog Vivado
Making the Basys 3 FPGA Portable Verilog Vivado
Переглядів 1212 роки тому
Making the Basys 3 FPGA Portable Verilog Vivado

КОМЕНТАРІ

  • @abuctf
    @abuctf 6 днів тому

    Cool!

  • @engineeringstudent2700
    @engineeringstudent2700 18 днів тому

    Can i interface a DHT11 temperature sensor on it?

    • @dajoma36
      @dajoma36 18 днів тому

      On what, this project? No. The circuitry is different for the DHT11 sensor. You would have to look at the DHT11 datasheet, which should provide information on interfacing with the sensor and timing diagrams, and then develop a circuit for the FPGA to read data from the sensor.

  • @gutierrezlopezjosue7196
    @gutierrezlopezjosue7196 21 день тому

    Hiiii, Would this project work for me, if I connect the Nexys as a slave and it uses a microcontroller (STM32F411E-DISCO) as a master?

    • @dajoma36
      @dajoma36 21 день тому

      I think it should work, if you input to the FPGA from the microcontroller through the PMODS, then direct those signals to the temperature sensor. One thing to be careful of is the voltages of the FPGA and microcontroller. The FPGA is designed for 3.3V, so a 5V microcontroller, such as Arduino, would break it. If this is the case, use a logic level converter. Good luck on your project.

  • @AyushiSaxena-n7b
    @AyushiSaxena-n7b Місяць тому

    i am not getting the waveform when performed in vivado

  • @CzechHouse-z9g
    @CzechHouse-z9g Місяць тому

    For readability " 50_000_000 - 1 " is better I think.

  • @SHIVARAM-tt5jt
    @SHIVARAM-tt5jt Місяць тому

    i tried same thing on nexys 4 board with the changes in constraint file but i was not getting the output can you help me with that bitstream also generated sucessfully

  • @AthiwatKongkaeo
    @AthiwatKongkaeo Місяць тому

    bro you are the GOAT.

  • @Gear4Auzaie
    @Gear4Auzaie Місяць тому

    whats the best budget/value board to get started other than the altera cyclone?

    • @dajoma36
      @dajoma36 Місяць тому

      As for the FPGA boards that I have experience with, I'd choose the Basys 3 because you can use as beginner and move into more advanced with it. For a real beginner-beginner board, the Go Board from nandland.com is a good choice.

  • @ChaseRace13
    @ChaseRace13 2 місяці тому

    Sir, Thank you so much for writing and breaking this code line-by-line. You are a gentleman and a scholar! You are making learning FPGAs not impossible!

  • @aleenamajeed6695
    @aleenamajeed6695 2 місяці тому

    Hi! I am trying to implement this code on a different FPGA board but am still using the same temp sensor. The board I am using is the Urbana board, and for some reason when I program the FPGA on Vivado, the only thing I read on the LEDs is 23 F and 0 C, and this is wrong for my room temperature which is 74 F, and this number doesn't change even when I apply heat to it directly. Does anyone have any advice or an idea on what the issue could be and a potential solution? Thanks so much!

  • @Is_The_Custom
    @Is_The_Custom 2 місяці тому

    Sir how can I do mapping for output variable "cols"? Should I type xdc file manually? I think I was be able to do mapping only for input variables. Thank you for your kind explanation.

    • @dajoma36
      @dajoma36 2 місяці тому

      Hi. I'm assuming that you want to output cols. What do you want to output to, LEDs? Yes, you would need to manually update the XDC file for the outputs.

    • @Is_The_Custom
      @Is_The_Custom 2 місяці тому

      @@dajoma36 Thank you for your kind explanation. Actually, I do not output cols directly to LEDs. What I have to do is to transform keypad signal into a 3-bit Opcode of ALU e.g. 0 into addition signal, 1 into subtraction signal. Thus, I have to put keypad signal into 7-bit variable and, using MUX, make the 7-bit value into 3-bit Opcode.

    • @Is_The_Custom
      @Is_The_Custom 2 місяці тому

      I thought row and col signal should be input of my ALU so that I can use the 7-bit signal from keypad as a Opcode, but somehow I failed. Your video showed me that "col" signal shoud be handled as "output variable, manually mapped in xdc file". I would be very grateful if you let me know I understand properly. Thank you for reading my comment in spite of my bad english, sir. :)

  • @ChaseRace13
    @ChaseRace13 2 місяці тому

    Great video

  • @ChaseRace13
    @ChaseRace13 2 місяці тому

    The z direction could be always in the positive direction because it’s always sensing gravity.

    • @dajoma36
      @dajoma36 2 місяці тому

      Great point!

  • @evanl734
    @evanl734 2 місяці тому

    What is the latency like? It looks like there is input delay or maybe delay from the screen. You would think the fpga itself would have almost no latency.

    • @dajoma36
      @dajoma36 2 місяці тому

      It's been a long time since I've made this video, but yeah, there isn't much latency in an FPGA.

  • @egegoksu9557
    @egegoksu9557 3 місяці тому

    Thanks

    • @dajoma36
      @dajoma36 3 місяці тому

      You're welcome. Thanks for your thanks.

  • @thanatosor
    @thanatosor 5 місяців тому

    Why don't we use AXI-Lite ?

    • @dajoma36
      @dajoma36 5 місяців тому

      I believe the AXI is only for use with Xilinx Zynq chips, which are SOCs (System on a Chip) that include FPGA fabric as well as processor fabric. AXI is used for the processor part.

    • @thanatosor
      @thanatosor 5 місяців тому

      @@dajoma36 so If I want to use it on Artix-7, I need a soft-core CPU like microBlaze right ?

    • @dajoma36
      @dajoma36 5 місяців тому

      @@thanatosor That's a good question. Sorry, but I don't have any experience with microBlaze and using AXI at all. I only know about it that it is used with the Zynq SOCs.

  • @Alan96555
    @Alan96555 6 місяців тому

    Did you know that you have a problem in your code? 26C should be 79F and 27C 81F (If rounded up). Do you know how it could be resolved?

    • @dajoma36
      @dajoma36 6 місяців тому

      Not sure what you are referring to. And, as the system works as designed, I don't see that there is any problem. Maybe you could provide more details to support your claim.

  • @timmorgan3673
    @timmorgan3673 6 місяців тому

    Hi David - Another excellent video - Just what I was after - Cheers :)

  • @waqasbhaat
    @waqasbhaat 6 місяців тому

    Sir i have learnt verilog Please recommend me projects on verilog Without using fpga

    • @dajoma36
      @dajoma36 6 місяців тому

      Well, if you are just starting out with Verilog, I recommend these projects, which are fun and interesting: -Decoder -Multiplexer -Flip Flop -101 Sequence Detector -Gray Code Counter Then maybe do some state machines: -Traffic Controller -Vending Machine -Voting Machine Each of these projects you can write Verilog circuits for and then verify the designs using a testbench written in Verilog. The Icarus Verilog software, with GTKWave signal viewer, can be very useful for simulating your designs. You can find it here: bleyer.org/icarus/ Good luck and have fun! David

    • @waqasbhaat
      @waqasbhaat 6 місяців тому

      Sir i will do projects on state machine After completing these projects I will inform you Thankyou sir

  • @reddyreddyhay333
    @reddyreddyhay333 6 місяців тому

    Sir what about Constraint file

    • @dajoma36
      @dajoma36 6 місяців тому

      Not sure what you mean, but the constraints file (.xdc) is in the Github page for this project.

    • @reddyreddyhay333
      @reddyreddyhay333 6 місяців тому

      ​@@dajoma36thanks for the video sir successfully completed project

    • @dajoma36
      @dajoma36 6 місяців тому

      @@reddyreddyhay333 Awesome! I hope it was helpful to you.

  • @clutchoney
    @clutchoney 6 місяців тому

    Nice one it is. By the way, this code only works on basys3? My fpga is other one:(

  • @yusufbingul467
    @yusufbingul467 6 місяців тому

    this is what we needed for our project. Thank you

  • @thanatosor
    @thanatosor 6 місяців тому

    Nexys A7 is basically upgraded version of Basys3 😂

    • @dajoma36
      @dajoma36 6 місяців тому

      Yeah, pretty much. It has a bigger FPGA chip with more logic fabric, and more widgets.

  • @thanatosor
    @thanatosor 6 місяців тому

    Which one is worthy for beginner to learn FPGA ?

    • @dajoma36
      @dajoma36 6 місяців тому

      The Basys3 is your beginner board out of the two here. The price is much less, also.

    • @thanatosor
      @thanatosor 6 місяців тому

      @@dajoma36 so what's Nexys Video for ?

    • @dajoma36
      @dajoma36 6 місяців тому

      @@thanatosor The Nexys Video has a much larger FPGA and many peripherals for doing projects with video, such as HDMI. It is also a very expensive board compared to the Basys3.

  • @RevanasiddeshU-e5n
    @RevanasiddeshU-e5n 6 місяців тому

    Really nice effort from you sir, can you please provide the testbench for this?

    • @dajoma36
      @dajoma36 6 місяців тому

      Thank you. The testbench has been posted on Github in the project folder.

    • @RevanasiddeshU-e5n
      @RevanasiddeshU-e5n 6 місяців тому

      @@dajoma36 Sir There is no testbench in Improved version folder

    • @dajoma36
      @dajoma36 6 місяців тому

      @@RevanasiddeshU-e5n I put the testbench in the folder with the original video. The i2c master files are exactly the same for the older video and the improved version. So, look for the testbench in the folder for the first video I did on the temp sensor using the Nexys-A7.

    • @RevanasiddeshU-e5n
      @RevanasiddeshU-e5n 6 місяців тому

      That testbench is not working for this improved version

    • @dajoma36
      @dajoma36 6 місяців тому

      @@RevanasiddeshU-e5n I'm sorry, that is the only testbench i have for this.

  • @akhil_rana
    @akhil_rana 7 місяців тому

    What is pullup true meaning with respect to sda direction ?

    • @dajoma36
      @dajoma36 7 місяців тому

      When no device is actively pulling the SDA line low, the pull-up resistor ensures that the line is at a high logic level (Vcc). This is crucial because it defines the idle state of the bus.

    • @akhil_rana
      @akhil_rana 7 місяців тому

      Thankyou ..It was I was missing in my project

  • @muhammedalikaya268
    @muhammedalikaya268 7 місяців тому

    sir, i 'm trying image load to vga monitor. In simulation, display variables are true but after the bitstream i can not see the image on the monitor. The monitor said 'no video signal'. What should i do? Can you help me, please?

    • @dajoma36
      @dajoma36 7 місяців тому

      I would recommend doing some troubleshooting. Look into the hardware such as cable and cable connections. To check your digital signals, you could use a logic analyzer on the VGA signals and verify if they are working correctly. Other than that, I couldn't tell you. If your circuit is simulating properly, and the bitstream is generated it is an acceptable circuit. Analyzing the signals coming from the FPGA to the monitor could help you find an issue or let you know that the problem is not this part.

  • @timmorgan3673
    @timmorgan3673 8 місяців тому

    Hi David - This is an excellent series of videos :) Dunno if you've come across Ross McGowan's "Design a CPU" series of videos or not ? These are also based on the "But How Do It Know ?" book, taking it to a 16-bit CPU, and then a Computer with a Keyboard/Monitor/Graphics Display. I found your UA-cam website as I was looking for help with getting my "Computer" Verilog code (based on Ross's courses) onto a an FPGA (Basys 3) - Your stuff has proved to be really helpful - So: "Ta Much" :) Cheers, Tim.

    • @dajoma36
      @dajoma36 8 місяців тому

      Hi Tim, thanks again for your comments. I have not heard of Ross McGowan's videos. I will have to check him out. Sounds like he took the CPU to a whole new level, and that sounds really interesting. Take care.

  • @timmorgan3673
    @timmorgan3673 8 місяців тому

    Hi David - Interesting - I wasn't aware of the issues that can result from using tri-state buses - Anyways: I'm still using a tri-state bus on my "Computer" & all seems well on the Basys 3 with CLK_E/CLK_S running at 1MHz ... But "food for thought" - Ta much :)

    • @dajoma36
      @dajoma36 8 місяців тому

      Hi Tim, interesting that you got the tri-state buses working. I was having trouble with them, and the comments I made about them came from my old college professor who said that to me. He is also the one who created the assembler for the project. Glad to hear everything is running well for you!

  • @timmorgan3673
    @timmorgan3673 8 місяців тому

    A very clear explanation & demonstration of the Control Unit - Good stuff :)

    • @dajoma36
      @dajoma36 8 місяців тому

      Thanks again for your comments! Glad it is helpful.

  • @timmorgan3673
    @timmorgan3673 8 місяців тому

    Hi David - Another very interesting & informative video - Thanks again for putting all your FPGA Videos "out there" - Cheers :)

    • @dajoma36
      @dajoma36 8 місяців тому

      Thank you for the feedback. I'm glad my videos are helpful and useful to people. Thanks for letting me know.

  • @denniswgm6526
    @denniswgm6526 8 місяців тому

    Many thanks David, I learnt alot from your video.

    • @dajoma36
      @dajoma36 8 місяців тому

      Thank you for the positive feedback. I'm so glad it was helpful to you.

  • @SouradeepSD
    @SouradeepSD 8 місяців тому

    Greatly helped me for visualising my outputs of hardware accelerator I made for image processing for my mtech project. Thank you for the clear and precise explanation.

    • @dajoma36
      @dajoma36 8 місяців тому

      Thank you for the positive feedback. I'm so glad that it was helpful to you.

  • @khevanapurohit4440
    @khevanapurohit4440 8 місяців тому

    Can I do it with uart protocol? If yes how?

    • @davidmarion8930
      @davidmarion8930 8 місяців тому

      No. The temp sensor is designed to communicate using I2C.

  • @jzie6615
    @jzie6615 9 місяців тому

    Sir can you please help me with mu project... So basically I'm doing home alarm system using basys3 verilog code and my professor ask me to add buzzer and ultrasonic sensor when switch is on so how will i connect these two in breadboard... Using the pmod ports... And do I need any other components... Please help😢

  • @zainmohd7
    @zainmohd7 9 місяців тому

    In your GitHub repository, the “flag.v” file is missing. Unable to run the simulation.

    • @zainmohd7
      @zainmohd7 9 місяців тому

      Please respond, urgently need it.

    • @davidmarion8930
      @davidmarion8930 9 місяців тому

      Ok. Sorry about that. Thanks for letting me know. As soon as I get a chance today I will put the file in Github.

    • @dajoma36
      @dajoma36 9 місяців тому

      flags.v has been added to Github.

  • @diegodiaz585
    @diegodiaz585 9 місяців тому

    Hello how would you turn on the decimal points to separate 100 sec , seconds, minutes, and hours

    • @dajoma36
      @dajoma36 9 місяців тому

      Hi. You would need to include the decimal point for the segments. So, the segment would be bit-width of 8 [7:0] with seg[7] being the decimal point, and include the dp in the constraints file from the master XDC file. And you would only want to turn that bit on for the anodes/digits that you want to turn on the dp, not every digit.

  • @jzie6615
    @jzie6615 9 місяців тому

    Can you please help me on connecting basys3 to adruino and from adruino with breadboard connect buzzer and ldr with led for some use in home alarm system

  • @abhishekss3560
    @abhishekss3560 9 місяців тому

    Hey great video, but i am stuck at one issue, i think maybe you can help me?

    • @abhishekss3560
      @abhishekss3560 9 місяців тому

      btw i have put an email to you! Hoping to hear back soon!

  • @timmorgan3673
    @timmorgan3673 9 місяців тому

    Great stuff - Most informative - Thanks for putting it out - Cheers :)

  • @b213videoz
    @b213videoz 9 місяців тому

    7:37 I do not understand line #22

    • @davidmarion8930
      @davidmarion8930 9 місяців тому

      A case statement is a more elegant and concise way for checking conditions, like if/else. Inside the parentheses () is the condition to check. On line #22 the condition being checked is a concatenation of two signals into one signal. Concatenating signals in Verilog uses curly braces {} with the signals being joined separated by a comma. Hope this explains.

    • @b213videoz
      @b213videoz 9 місяців тому

      @@davidmarion8930Sorry, no it doesn't explain. I do understand how CASE works what I do not understand how the address is being evaluated with {row, column} You just so casually skipped it over by throwing "concatenation". How ? Does it really do + ? Then it makes no sense address = row + column. I'm lost. address = row * <size of row> + column - that would make sense, but you use {row, column} and that seems to work.

    • @dajoma36
      @dajoma36 9 місяців тому

      @@b213videoz Sorry, I guess I assumed that you might know what concatenation is. It is essentially joining the two signals into one. So, the bits of row and the bits of column will be joined into one, side by side, and evaluated as one for the CASE. It is not addition, nor multiplication, it is just placing them side by side. Example: if row == 0010, and if column == 1101, then the concatenation, i.e. joining, of the two, {row, column} = 00101101. Does this explain?

    • @b213videoz
      @b213videoz 9 місяців тому

      @@dajoma36Thank you, David. Yes, of course I know what concatenation is but I know close to nothing about Verilog and FPGA programming in general 🙂 As it turned out in that particular case you had a merge of two 4 bit bit pieces into an 8bit one, which resulted in 4 bit shift to the left + 4 bit addition which effectively is the same as high_4_bits * 32 + low_4_bits, only much more efficiently of course. My point is that was a non-trivial piece of code deserving some explanation yet it was just skipped whereas some trivial and obvious bits were explained too well. Anyway your examples (I mean code) are extremely easy to follow, I just bought your paper book at Amazon, I do hope there are some good explanations there.

    • @davidmarion8930
      @davidmarion8930 9 місяців тому

      Sorry I didn't explain everything. There's alot to cover in some of these videos, and I do try my best. I appreciate your feedback. Thanks for buying my book. I do hope it serves you well.

  • @b213videoz
    @b213videoz 9 місяців тому

    Excellent stuff! Thank you, author - the best tutorial on the subject I've managed to find so far. 10:00 this is what I don't understand though: the wall as per your code should be on the left side, its X coordinate is something around 35 BUT in your video it's on the right side of the screen. HOW ?

    • @NVISH-kb4nc
      @NVISH-kb4nc 7 місяців тому

      whole video is mirrored i think

    • @b213videoz
      @b213videoz 7 місяців тому

      @@NVISH-kb4nc Yeah, I thought so, then the author clearly mentioned in some other video.

    • @NVISH-kb4nc
      @NVISH-kb4nc 7 місяців тому

      @@b213videoz oh that’s great

  • @NaniGurrapu
    @NaniGurrapu 9 місяців тому

    Their is no testbench code in GitHub

  • @pankajkumarsingh487
    @pankajkumarsingh487 10 місяців тому

    bitstream generated but not working on board

  • @xmod2157
    @xmod2157 10 місяців тому

    please make a video on 8bit risc V implementation

  • @dajoma36
    @dajoma36 10 місяців тому

    @hardcode I received your message, but for some reason I cannot directly respond to you. As for your issue, why are you using 9600 baud? That is for a serial communications. All I did in the video was set up a simple 1Hz tick from the Arduino (LED blink sketch) to drive a counter on the Basys 3 FPGA, and then use a 7-segment display driver to display the hexadecimal value on 1 digit of the 7-segment display. If you are using serial communications at 9600 baud, then you are doing something different from what I did, and it is hard for me to know what your issue is. If you would like more assistance with your project, please email me with more details so that I can understand what you are trying to do and maybe help you out.

  • @Unknown101-ol7op
    @Unknown101-ol7op 10 місяців тому

    worst

  • @Unknown_me_you_all
    @Unknown_me_you_all 10 місяців тому

    worst video

  • @priyankamaharana3005
    @priyankamaharana3005 11 місяців тому

    After giving the xdc file in vivado, the bit stream isn't generating. What should i do?

    • @dajoma36
      @dajoma36 11 місяців тому

      Hi. Forgive me if I am being presumptuous. In order to make this work you need more that just the xdc file. You must add the Verilog files as source files and add the xdc file as a constraint file. Then, run synthesis, run implementation, and generate the bitstream.

  • @jermynlau6188
    @jermynlau6188 11 місяців тому

    Hi, I found this this is amazing and useful!!! But I have another question, if I want to input more than 4 characters on the keyboard, what should I modify🤔🤔🤔 Thank you so much!!!

    • @dajoma36
      @dajoma36 11 місяців тому

      You would need to make the FIFO capable of holding more than 4 characters.