Preset and Clear Inputs in Flip Flop
Вставка
- Опубліковано 5 жов 2024
- Digital Electronics: Preset and Clear Inputs in Flip Flop.
Contribute: www.nesoacademy...
Website ► www.nesoacademy...
Facebook ► goo.gl/Nt0PmB
Twitter ► / nesoacademy
Pinterest ► / nesoacademy
you know sir ... our techers advice us with your lectures ... thank you so much
That's why, tell your teacher to say loudly.. India is Great 🇮🇳
@@bhargavpratimsharma2024 what did you want to say?😂
@@PriyanshuSharma-ey3bc 😉😉
@@PriyanshuSharma-ey3bc exactly lol
When I hear that Neso intro I know I'm gonna gain some mad knowledge
The same is with me... thanks NESO
Make India Great Again🇮🇳
Thanks a lot. I appeared in gate in 2017 and lost the notes. Now EEE is my optional in CSE. Thanks for make me remember the concepts easily.
What happened to you cse bro?
Thank you for the video. Although not common, there are times when both preset and clear are brought low at the same time. This IS defined as Qn and /Qn both outputting HIGH. While using spare gates, a flip flop may be used as an inverter by tieing D, CLK, and CLR to low, and any signal on PRESET will end up inverted on Qn. -try if you ever need one inversion before using the second flip flop of a 74xx74.
if clear is 0 than Qn' is 1 but Qn is not necessarily 0 because it depend on S (think if S =1 and clk =1) .Sir please clear my doubt
Setting the clear to 0 and the preset to 1 (or vice versa) changes the circuit so that it only has one "stable" state. It can momentarily give Q = Qbar = 1 as output, but only when clk = 1 and S = 1 (or R = 1 for preset = 0, clear = 1), which it usually will not. (I put "stable" in quotes because technically having clk set to 1 is possible, but it's just not how you're supposed to use the circuit.) [Disclaimer: I'm just an undergrad struggle through this shit with the rest of y'all. I could very well be wrong.]
you are doing great work sir! keep it up..... much respect!
I think it would be better for me to drop out from my college.......................Idiotic system when we can learn such high quality content for free ,then just think what the quality of education should be in the colleges........😡😡😡😡
I also feel the same thing sometimes....😂😢😅
Drop out ho gaye kya
Whenever I hear that initial music feeling of braking bad came in my mind
Regarding active high and active low confusion, think in terms of High and Low instead of 1 and 0. In active low logic(0=High and 1=Low),and in active high(1=High,0=Low).Active high circuit implies circuit is functional only when input is 1. Similarly, Active low circuit implies circuit is functional only when input is 0. Here, preset and clear are active low, meaning preset will be high(functional when we have 0 input in it), and will set Qn=1. And if clear is also 0(here high), it will again try to reset Qn, i.e. will try to make Qn=0. So this(Preset,clear=0,0) is not used. While Preset=1(low), it will be non functional,same impiles for clear.
Thanks a lot bro! That was a pretty good explanation. You helped me remove whatever doubts I was having :)
very clear explanation thanks bro
what about when r=0 and preset is 0 then qn complement will be 1 and qn will also be 1
Much love and appreciation from Tanzania 🙏🏽🙏🏽🙏🏽🙏🏽
Sir You are the best lectures, I have ever seen in my life. Sir please continue this chanel and keep help us.
your videos are very precise and nice
Yes as mentioned in comments. The circuit diagram used in video is INCORRECT.
Just google it you will find correct diagram or atleast something from where you can approach further...
sir your lectures are very good and i find them very concise.
thank you.
best channel i swear , thanks a lot thankss thanksssss 🙌🏻🙌🏻
I understand that: When Clr = 0 then not-Q is directly 1. However from this point, not-Q is fed back to the upper NAND gate where Pr = 1 then 1 AND 1 is 1, so the output of the upper NAND gate (Q) is not directly 0 but dependent on the front NAND gate's output where S and Clk are inputs. Can u please explain how we get directly Q = 0 when Clr = 0? Thank you
I also had same doubt it will depends on s if clk is present ..
I am having the same doubt
for s=0, R=1, Clk=1,Pr=0,CLR=1, both outputs will be 1, is it right?..it means it will depend upon input and clock status too..please explain
Can u please upload a video on presettable programmable counters and also down counting in asynchronous counters from any value
I was confused when we made the truth table. I understand the way the preset and clear inputs are effecting the circuit, but I think we switch our analysis from the blk diagram and the circuit at the same time, because when preset is 0, it is inverted on the blk diagram so it is a 1, and it doesn't effect the NAND gate. in the same way, when clear is 0, it is inverted to a 1, and so that would also not effect the NAND gate. If i looked at it in this way, that would make the truth table backwards. I hope someone could clarify this mix up.
actually i have the same confusion right now any explication for me pls?
Sir how u get such depth knowledge,from just reading book I can't get so much understand in like you do in your video s ,pls reply your secret sir
coz NESO is NESO..........
Neso best digital site. I always get full marks
You're a lifesaver. Thanks!
man, u r the god of elctronic for me, keep it up bro, ur videos are very useful, please don't you stop uploading video, thank you very much
Thank you Neso,,,um watching your videos everyday
Very helpful sir
So set and reset can be used only when the clock is 0.
If not, please explain how clear is setting Q to 0 while the CLK and S are 1.
dude just focus on the nand sr latch on the very right... if one of the NAND's inputs is 0, the output will definitely be 1. So.. Where's the "clock" in this equation.. Nowhere... Hope you got it.
@@batikanboraormanci7954 but what if in top right nand gate, preset is 1 CLR 0 ,so two inputs of the nand gate are 1. The third input HAS to be 1 so clock input HAS to be 0. Therefore clk 0 is necessary I guess
@@momentodebruh7300 if preset is 1, it is the same as no preset existing at all. It wont change the way the system works a bit.
If clear is 0, then no matter the clock or anything, the nand gate on the right bottom corner will be 1.
So if the preset is one, then its already not changing anything, the ff will function normally on that side. The clock's impact will be same as expected.
if clear is 0, as QNcomplement becomes 1,
Rule 1 : you dont turn both preset and clear to 0 at the same time, that just breaks the system, so preset stays 1
2: if set and clock are also on, QN will be 1, meaning that the ff is misfunctioning, because you tried to "set" and "clear" at the same time.
With or without the clock, the S will be the one breaking the system
So the statement "clock has to be 0" is wrong
Right is " s and clear dont work together, logically or practically"
@@batikanboraormanci7954 cool thanks
That is correct, Clock has to be zero.
There is a misconception in the above video and it precisely has to do with the clock signal.
First i think we can all agree that:
If SET is 1 and CLK is also 1 then the output of the TOP LEFT NAND gate is 0, which is also one of the 3 inputs of the TOP RIGHT NAND gate ------> If one input of a NAND gate is zero then its output Q, will always be 1, no matter what the other inputs are doing. So for the SR FF shown in the video above, during the time SET is 1 and CLK is also 1, the SR FF cannot be cleared !
Note: we are ofcourse assuming CLK is a proper 50% dutty cycle ON, 50% dutty cylce OFF traditional clock, just like all clocks.
So for the SR FF in the video, as it is drawn, CLR and PRST are not Asynchronous, because of the 50% ON clock duration.
For CLR and PRST to be trully Asynchronous, the SR FF MUST be EDGE TRIGGERED ! (In this case Positive edge triggered)
That way when the "clk" input to the FF is pulsed (from 0 to 1), it will immediately return back to 0 instead of staying at 1 for 50% of the clock period. But the edge triggering circuit is not mentioned in the video...
This is the critical detail the lecturer forgets to mention : /
SIR, Truth table which is taught in this video is correct in two cases
1)either clock =0
2)or R & S =0
I am thinking in this way frnds. Pls correct me if I wrong
Thank you so much for the video. Bu what about Master-Slave triggers? I saw that you need to put Preset and Clear both in Master and a Slave. Why can't we just put them only in Slave, which gives as true Q and nQ outputs?
it's not so clear how could be that if we have Preset = 0 (with Clear = 1) we have Qnot = 0 in every case. It's not possibile if lowermost input of latch is 0, because in that case we have Q = notQ = 1, which is an invalid state. Is it possible that Preset works only when clock is low? because in that case it could be...Thank you
I have also got same doubt
can anybody help me? in this video, the teacher shows the block as active low and the table is for active low right? then how about active high? where preset and clear doesnt have bubble? what is the values on the table?
really good explanation
your videos are very precise and nice ... it is very useful to clear the concepts
thank you sir
good work in explaining this, you are better than my doctor. keep up the good work :)
always watch neso videos on 2x
Amazing explanation sir 😊
Thank You Sir
Can't thank you enough
YOU ARE THE BEST MAN
everything is perfect sir.
When "Not Used" is mentioned, it means we literally want to avoid those kinds of signals on such circuits or else they would result in unprecedented outputs right?
Can you please explain the active low and active high outputs of s and r ff and CLR=1 and PRE=1. At that condition how it will work
I have a Question. Above, it was said that when Preset = 1 and Clear = 0, Q' will be 1 and Q = 0. However if i set S = 1 and CLK = 1, i would get 1 for the Q ( because the inputs are : 1(Preset), 0(NAND of S(1) and CLK(1)), 1(Q') ). Are you implying that the inputs are actually neglected ?? Anyone care to explain?
i have the some question
thank you sir
i have a doubt.in practical experiments,how do we connect preset and clear to ic chips in a bread board
how can you assume q and q bar will be complement of each other when u set clr or preset at 0, without knowing the value of S and R? plz clear this confusion.
arindam pal clock is 0 when preset and clear are used that is circuit is in inhibited state.... because it is used to set value when power is just turned on
What's the use of present and clear and why they are operated active low???? Plzz reply
By using preset and clear we can make flip-flops set to 0 or 1
You have very good videos, Sir, ,thanks!
When Pr=1, Clr=0, Qn(bar)=1. But how Qn goes to 0? As, NAND gate has 3 inpus. For Qn to be 0, all these inputs must be 1. Qn(bar)=1, Pr=1, what about the 3rd input(middle one)? How you can ensure that this is always 1? Please explain
Vartul Sharma i have the same question with you. Plz someone answer this question. Why q and qbar should be always complementary?
well preset and clear are used to set state when circuit is just switched on so no input is considered from the prevois part and so only 2 ones are required to make q bar zero
so in simple terms clock is 0 when preset and clear are used
@@sarthaksuper284 Nice Sarthak you help in my doubt clearification
In some circuits clk is bubbled and in some ckt clk is not bubbled is there any logic reason ?
Bubbling usually indicates the use of a not gate or inverter
well explained, thank you
1) Bring a connection from preset, give it at 2nd i/p NAND gate on LHS.
2) Bring a connection from clear, give oy at 1st i/p NAND gate on LHS.
NOW THE CIRCUIT IS CORRECT...
Sir,How Qn will be 1 for prst=0 and clr=1 for clk=1 & R=1.
when u make clear=0 qbar becomes 1. preset is obviously 1 when clear=0. so q will become 0 only if the output of s and clk nand gate is also 1, because output of nand gate is 0 only if all inputs are 1. but how are you sure that the output of s and clk nand gate is always 1. what if i'm trying to set the output when clk is high???
Thank a lot sir it helped me a lot
what's different between sync and Async inputs ?
Question: from the block diagram, isnt it that when clear =1, Qn=0 and when Preset =1, Qn=1? because for the block diagram there is an inverter attached, so when clear =1, the circuit is actually getting 0, making Qn=0?
***** If we are not taking the complement of preset, how do we get (preset = 0 => Qn = 1)? We need to look at the the output of (S'+clk') to determine Qn, right?
Also, I'm a bit confused about the active low input, if you have a video explains this concept please provide me with its link in the comments box. Thank you!
i gone through u r videos amazing,but preset=0 and clear=0 in nor gate entire thing changes once explain it
It's total confusing can anyone explain it briefly.... pls
THANK YOU SO MUCH
When clear is 0, Qn_bar is 1 but for Qn to be 0 at this time S should be 0, so how is it independent?
Sir...as u said that
In block diagram it is low active pins ...means if we give PR =1 & CLR =1 than ultimately the input to FF is 0 & 0..... and then it is condition of not used......
Then how it is possible.....
Sir I'm in confusion ....
Plz clear the doubt....😊
Thanks
since both preset and clear are active low inputs, if they are high then they won't get activated and hence the flip-flop will work in a synchronous fashion. Synchronous means that input data will be tranferred to the flip-flop output only on the trigerring edges of the clock pulses.
when PR=0, preset pin will get activated and output will become HIGH and when CLR=0, output will be zero and hence flip-flop will work asynchrously. Asynchronous means that any of the asynchronous inputs(PR,CLR) can affect the state of the flip=flop independent of the clock.
Hope your doubt is cleared.
Sir,
Slease upload the videos for asynchronous sequential circuits
Sorry, but I'm not so much cleared about preset and clear from this video. I want to know about its applications, and why do we use them along with how does it work actually. Will you please let me know by creating a video for this shortly?
big thanks
hii sir, sir do memory cards also have flipflops i.e d flipflops inside but if we remove power supply Vcc how do a d flipflop stores the data becoz in practical case we remove memory cards n pendrives but it still holds data how does this stuff works.
I don't understand what is meant by "active low" , would you pls show me where did u explain it!? Cause I'm focusing only on sequential circuits in this semester .
And how to make a timing graph too ! With showing the difference between FF in it ♥
Sure I must thank you so much for your efforts , you do help me to understand more than my lectures do 💪👏
Active low means that when the input is 0 the circuit works. Active high, which is the generally used condition, is when the circuit works on the input 1
hello..sir can you please upload the lectures for HDL implementation of digitat electronics
What is the difference between Clear and clear baar
sir which one is lecture no 121???
one after the clock lecture......
Can u please explain the 0 1 state again in more detail ........relating the clear=1 as an input ?
Do you have Lectures about Trafic Light etc???
THANK UUUUUUUUUU SIR
Clear 1 must give Q=0 right?
Is the preset and reset same as the set and reset???
truth table will be same for NOR gate?
what if clear=0, and preset=S=Clk=1? I think both outputs will be 1 in this condition.
Hiii Neso academy your lectures are quiet good. I have problem in understanding in STATIC Timing Analysis(STA).Can you please make a video on that topic
can we also use reset in the place of clear?
Thanku sir
what about the preset and clear in case of JK flipflop?? because u have only shown for SR flipflop!
It has the same effect.
It just do the same as in SR flip flop.
when preset=0,Q=1&Q'=0 and when clear=0,Q=0&Q'=1
As we infer from the diagram it does not depend on the S and R value as well as J and K value
I am not clear as how NAND gate is having 3 inputs??
u r best...
Oh I messed up on my truth table for tha NAND gate. thanks
sir please tell us how to access these notes
I didn't understand what happens when preset = 0 and clear =0 ? can u please explaint it shortly in the comment ? Thanks
in that case we force as output of nand gates both 1, which is an invalid state
what if preset is 1 and clear is 0 and S =1 clk =1 ,,,, as clear =0 Qn' =1 and as clk = s =1 hence Qn=1 . So contradiction is Qn=1 and Qn'=1.
Yes I am caught up in the same thing did you find an answer to this question? Please will be very thankful
Isn't this a latch??
how does clear being equal to zero affect Qn. I see that it would force Q'n to 1 but not how it would do anything to Qn.
because Q'n is complement of Qn . Which will set it to 0 as it's complement is 1.
ANUSHKA SINGH 15BEC0306 why q & q bar should be complememtary?
anyone knows how to construct clear using circuitverse?
sir why we call them preset and Clea r
thanks a lottttt
How can you put preset and clear in a NOR latch...
AND AND NOT
Doubt Cleared 😅
You said it wrong at 3:35.
We will consider it as active high, because if we will take it as active low(in your case), then we have to revert the given values.
Active low : (PRE)' (CLR)'
Active High: PRE CLR
won't it ?
I think that when preset= 1and clear= 0 then Q should = S
Thank you!
Do you go to college?
everything was going good until you wrote that block diagram according to you if pre =0 then Qn =1 but bubble of the block diagram will make pre =1 and how qn =1 HOW? and we know in nand gate the if any one input is low then output is high then how pre =1 will make output =1????????????????????
The bubble isn't a NOT gate, it is just there to represent the kind of input that makes it active.
@@akarshchaturvedi2803 ya actually real confusion was that there wasn't a bar over PRESET and CLR
That's what I call an explanation, not that difficulttttttttt !!!!!!! ghhghghg certain prof are terribleeee
I get it sir😎
I love your lecture but the only thing i find troubling me is the speed at which you teach. Even with the platback spped of 2X , i find it slow. Please teach a little faster.
"Even at playback speed of 2x, i find it slow" - Ye thoda zyada nhi hogya ?
@ ekdum bhi nhi bro mai khud 2X mai dekhta hu fir bhi slow lag rha hai kya kru?
Lecture Number ????
plz
Thanx