Lecture-19|VLSI System Testing| Design for Manufacturability and Boundary Scan (JTAG)
Вставка
- Опубліковано 10 вер 2024
- Subject - VLSI System Testing
Semester - II (M.Tech, Electronics & Telecommunication)
University - Chhattisgarh Swami Vivekanand Technical Univesity (CSVTU), Bhilai.
Topic - Design for Manufacturability and Boundary Scan (JTAG)
Faculty - Prof. Ashish Tiwari (PhD*, M.tech (VLSI Design), B.E. (Electronics and Telecommunication), Senior Member (IEEE), Life Member (ISTE).
You will get the answers to these questions in this lecture:
What is design for manufacturability? What are the different criteria underneath it? Why we need boundary scan technique? How it is done?
