System verilog / Verilog Interview QA Part 1

[@rohitth9101]

module (in, clk, reset,out);
input in,clk, reset;
logic [9:0] count;
output logic out;
logic out_reg;
assign out_reg = (count >10’d511)?in:out;
//registering to avoid combinatorial loop
always_ff@(posedge clk)
begin
if (! reset)
out

[@TechnicalBytes]

Dear Rohit, while generating variable out_reg como loop is already generated.

[@rohitth9101]

@@TechnicalBytes yes, the combo loop is generated , what I meant is by registering I am avoiding any case which could cause glitch in the circuit . Isn’t it?