#2 : Verilog Review

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  • Опубліковано 31 жов 2024

КОМЕНТАРІ • 7

  • @vitorbarbosa3272
    @vitorbarbosa3272 8 місяців тому

    Great class! One detail at 22:10, I believe "assign signal = x" is for continuous assignment. For blocking assignment we should drop the "assign" keyword.

  • @yousifhazem1416
    @yousifhazem1416 8 місяців тому

    Great lect. thank you.

  • @autumnfox1215
    @autumnfox1215 3 роки тому +2

    Hello! Very interesting course, is it possible to follow it with De10-Nano kit?

    • @hunteradams9430
      @hunteradams9430  3 роки тому +3

      Based on what I read about the De10-Nano, yes I believe so. Some of the i/o interfaces that we use in this course (in particular the audio CODEC and the video out) are not available on the De10-Nano, but it seems that everything else translates. That being said, I haven't played with the De10-Nano yet, so I don't know for certain.

    • @autumnfox1215
      @autumnfox1215 3 роки тому

      @@hunteradams9430 Thank you!

  • @tharalpius778
    @tharalpius778 2 роки тому +1

    assign target = condition ? value_if_true : value_if_false;
    This is the syntax for conditional assignment
    I think you got it wrong