Counter Designing in 8085 Microprocessor: Program and Techniques | 8085

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  • Опубліковано 15 лис 2024

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  • @Djajdevil-xp3hn
    @Djajdevil-xp3hn Рік тому

    sir for JNZ loop1 there is 10 T/7T states so for calculating delay you haven't done -3T at the last you added 10T states but if zero there will be 7T states so -3T also you will do. please reply

  • @venkatarohitpotnuru38
    @venkatarohitpotnuru38 Рік тому

    sir ANA H na why ORA

    • @jimmoriarty5993
      @jimmoriarty5993 23 дні тому

      because we have to check if the HL register pair together is zero