I love how this tutorial is super duper easy to follow. Although a little slow for some people, it's great for dummies like me who need absolute every step in order to learn things.
Hi Jonas, I just wanted to say that this tutorial series has been incredibly helpful for me. I struggled a lot with VHDL initially despite having a lot of prior knowledge in programming and having taken 2 semesters of digital design. I love your style of presentation: very concise and systematic and helped me figure out what I was doing wrong in trying to learn the language. Thanks for all the effort!
very use for me .... especially error : "empty source files " occur my program .after watching your video i solve the problem. thanks a lot , keep going on
When I try to save the project, the options "Save" and "Save as" aways remain greyed out. Is there a way to save a project? Sometimes it will come back where I was if I close it and open it up again, but it gets really complicated if I'm running more than one project. Usually, because of this, I will have to create a new project whenever I open up ModelSim after having closed it.
The "Save" and "Save as" are related to the built-in file editor in ModelSim, not for saving the project. The ModelSim project is auto-saved to an .mpf file in the folder you created it in the first place, that's why it pops back up when you open ModelSim. Try to double click on a .vhd file within the project explorer in ModelSim, and you will se what I mean. Then, the "Save" option won't be greyed. To open another auto-saved project, go to file->open. Select File type->Project Files, otherwise you won't see the project file in the explorer. Finally, you can select the .mpf file to open the project. A bit cumbersome, but that's how ModelSim is.
I should say that even if this is the first tutorial of vhdl, there is still a lot to explain before you get to tb and more. This is for someone who knows how the structure should look like and then it is time to practice!
There are many different opinions about how you should teach VHDL to newbies, and they are all right from their standpoint. What I find is that almost all who start with FPGAs have prior programming experience. That's what I want to leverage by starting with Hello World! and only working in the simulator during the first lessons. And to do to that, we have to create a "testbench" even though we are not testing any module.
I'm not entirely sure what Xilinx left out from the lab edition, but don't think it includes the VHDL simulator. That makes it useless for developing or learning VHDL. It's meant for debugging in the lab when you already have the code, I believe. Why not download the free Questa (ModelSim) simulator from Intel? Check out my blog post to see how: vhdlwhiz.com/free-vhdl-simulator-alternatives/
Try to delete the compile library files with the command "vdel -lib work -all" and recompile. If that doesn't work, recreate the project. Possibly move the files to somewhere with a path containing no spaces or special characters. It's been a problem before but not with the latest versions of Questa.
It can be a number of things. Try to delete and recreate the 'work' library by entering these commands in the ModelSim console: vdel -all -lib work vlib work And recompile. Also, don't use spaces in your VHDL file.
I'm unsure what you mean, but I will try to answer. You can print the value of IEEE library types like this: --- signal my_sl : std_logic := '1'; begin process begin report "my_sl = " & std_logic'image(my_sl); wait; end process; --- std_logic is an IEEE type, and the output will be: ** Note: my_sl = '1'
@@VHDLwhiz thanks this helped and I was referring to vivado where you have to declare libraries and different packages to work with here I didn't see any mention of the library that's why I asked since I seen you use it. Thanks for the answer and keep doing god's work 😊
@executorarktanis2323 Oh, I see. I didn't import any libraries in this example because we used no data types. VHDL only has a few built-in types like "bit" and "integer". Otherwise, you must import IEEE as you discovered.
When I load this code into a real FPGA, How this FPGA sends "Hello World!" string to outside? I did not understand how this code work in real use case?
This code is only for simulation. The report statement only prints to the simulator console. Showing the message on a screen from an FPGA requires a lot of other infrastructure. Perhaps you would like to join my Facebook group where you can ask questions like these facebook.com/groups/vhdlwhiz/
Hello Sir, I did exactly the same steps as u explained but when I arrive to section start simulation, it comes the error message "cannot read stratup(-L):no such element in array" i couldn't fix it. If you know, would you please give a tip. Thank you
I love how this tutorial is super duper easy to follow. Although a little slow for some people, it's great for dummies like me who need absolute every step in order to learn things.
Hi Jonas, I just wanted to say that this tutorial series has been incredibly helpful for me. I struggled a lot with VHDL initially despite having a lot of prior knowledge in programming and having taken 2 semesters of digital design. I love your style of presentation: very concise and systematic and helped me figure out what I was doing wrong in trying to learn the language. Thanks for all the effort!
I'm glad I could help! Visit the VHDLwhiz.com website if you haven't already. 🙂
I love your way of teaching, you show us errors and how to fix them
Thanks! I'm glad you liked the video.
Just finished all 24 vids... this is a great little introductory course... I'm looking forward to the Fast-Track, should be fun.
Congratulations! Good work.
very nice introduction to VHDL using ModelSim - that is what I needed :)
Thank you so much! I have zero experience with any sort of programming but I have to do this for college so I was at a loss until I found this
very use for me .... especially error : "empty source files " occur my program .after watching your video
i solve the problem. thanks a lot , keep going on
I'm glad I could help :)
lol I thought you were gonna build a 8bit CPU, send it to FPGA and then write an OS then C compiler to print hello world :)
That sounds like fun! But maybe not as somebody's first VHDL program. :)
yeah that's too complicated! I am here to build Skynet....🤷♂️
great explanation! Thank you so much
Thanks! Greetings from Mexico.
Very clean introduction, thank you.
When I try to save the project, the options "Save" and "Save as" aways remain greyed out. Is there a way to save a project? Sometimes it will come back where I was if I close it and open it up again, but it gets really complicated if I'm running more than one project. Usually, because of this, I will have to create a new project whenever I open up ModelSim after having closed it.
The "Save" and "Save as" are related to the built-in file editor in ModelSim, not for saving the project. The ModelSim project is auto-saved to an .mpf file in the folder you created it in the first place, that's why it pops back up when you open ModelSim. Try to double click on a .vhd file within the project explorer in ModelSim, and you will se what I mean. Then, the "Save" option won't be greyed.
To open another auto-saved project, go to file->open. Select File type->Project Files, otherwise you won't see the project file in the explorer. Finally, you can select the .mpf file to open the project. A bit cumbersome, but that's how ModelSim is.
@@VHDLwhiz
Thank you. This will save me quite a bit of time over the long run.
I am working in a project, in which I use FPGA for simulation acceleration. There I need some help with hdl coding for FPGA and Nios II processer
What sort of acceleration are you planning to do with the FPGA?
I should say that even if this is the first tutorial of vhdl, there is still a lot to explain before you get to tb and more. This is for someone who knows how the structure should look like and then it is time to practice!
There are many different opinions about how you should teach VHDL to newbies, and they are all right from their standpoint. What I find is that almost all who start with FPGAs have prior programming experience. That's what I want to leverage by starting with Hello World! and only working in the simulator during the first lessons. And to do to that, we have to create a "testbench" even though we are not testing any module.
can I use vivado LAb edition for learning vhdl
I'm not entirely sure what Xilinx left out from the lab edition, but don't think it includes the VHDL simulator. That makes it useless for developing or learning VHDL. It's meant for debugging in the lab when you already have the code, I believe.
Why not download the free Questa (ModelSim) simulator from Intel? Check out my blog post to see how: vhdlwhiz.com/free-vhdl-simulator-alternatives/
The Problem with me " Error loading design" what is wrong 😢
Try to delete the compile library files with the command "vdel -lib work -all" and recompile.
If that doesn't work, recreate the project. Possibly move the files to somewhere with a path containing no spaces or special characters. It's been a problem before but not with the latest versions of Questa.
Hello,
When I do simulate it seems , error loading design. What is the What is the solution, please
It can be a number of things. Try to delete and recreate the 'work' library by entering these commands in the ModelSim console:
vdel -all -lib work
vlib work
And recompile. Also, don't use spaces in your VHDL file.
Does it work with IEEE libraries?
I'm unsure what you mean, but I will try to answer. You can print the value of IEEE library types like this:
---
signal my_sl : std_logic := '1';
begin
process
begin
report "my_sl = " & std_logic'image(my_sl);
wait;
end process;
---
std_logic is an IEEE type, and the output will be:
** Note: my_sl = '1'
@@VHDLwhiz thanks this helped and I was referring to vivado where you have to declare libraries and different packages to work with here I didn't see any mention of the library that's why I asked since I seen you use it. Thanks for the answer and keep doing god's work 😊
@executorarktanis2323 Oh, I see. I didn't import any libraries in this example because we used no data types. VHDL only has a few built-in types like "bit" and "integer". Otherwise, you must import IEEE as you discovered.
I am working on Smart fusion A2F500Mg484 board and libero soc v11.9 software. I have some doubts, will you help me out for that?
You can try to ask in my Facebook group: facebook.com/groups/vhdlwhiz/
so eye opening! great job
please make VHDL
verification videos
When I load this code into a real FPGA, How this FPGA sends "Hello World!" string to outside? I did not understand how this code work in real use case?
This code is only for simulation. The report statement only prints to the simulator console. Showing the message on a screen from an FPGA requires a lot of other infrastructure. Perhaps you would like to join my Facebook group where you can ask questions like these facebook.com/groups/vhdlwhiz/
Hello Sir, I did exactly the same steps as u explained but when I arrive to section start simulation, it comes the error message "cannot read stratup(-L):no such element in array" i couldn't fix it. If you know, would you please give a tip. Thank you
Exactly what i needed
Nice. Thanks!
Thanks Jonas
excelent! thanks!
mozna latac samochodem. kto komu zabroni. mozna tez w vhdl pisac hello. skoro ktos uwaza ze to ma sens. to ok.
neko sa fera