How to use Port Map instantiation in VHDL

[@AhmadAsmndr]

Thank you very much. Very helpful Video!

[@broytingaravsol]

why can't the defined entity content built in the same console for port map?

[@iloveukraine-subscribe1kgo822]

I understood your code.. i was referring ur example with another one in my university lab. Here they have written port declaration under architecture, but again they have written signal inputs with the same name. It is really needed to write port in testbench or signal is enough?
And u didn't write port declaration under your tb. Thats y I got this question.
ARCHITECTURE behavior OF wb_switch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wb_switch
GENERIC (
memaddr : generic_addr_type := CFG_BADR_LED;
addrmask : generic_mask_type := CFG_MADR_LED
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
btn : IN std_logic_vector(6 downto 0);
sw : IN std_logic_vector(7 downto 0);
wslvi : IN wb_slv_in_type;
wslvo : OUT wb_slv_out_type
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal btn : std_logic_vector(6 downto 0) := (others => '0');
signal sw : std_logic_vector(7 downto 0) := (others => '0');
signal wslvi : wb_slv_in_type;
signal slvi : wb_mst_out_type;
signal slave_out_data: std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal wslvo : wb_slv_out_type;

[@kenturkey1971]

Clarity on which is the local and which is the entity signal would have been nice.

[@VHDLwhiz]

They behave identically. The only difference I can think of is that you can't write to "in" mode signals. If you want to distinguish them from local signals you can prefix their names with something, "in_" or "out_", for example.

[@kenturkey1971]

@@VHDLwhiz I did a little experiment, where the mux is instantiated. The entity signal must be on the left, and the local must be on the right. That may be obvious to someone who's done it for a while, but I wasn't clear since all the variables are named the same.
("l_" is my local signal prefix in the Tb)
This fails:
i_Mux1 : entity work.mux(rtl) port map(
l_Sel => Sel,
l_Sig1 => Sig1,
l_Sig2 => Sig2,
l_Sig3 => Sig3,
l_Sig4 => Sig4,
l_Output => Output
);
This succeeds:
i_Mux1 : entity work.mux(rtl) port map(
Sel => l_Sel,
Sig1 => l_Sig1,
Sig2 => l_Sig2,
Sig3 => l_Sig3,
Sig4 => l_Sig4,
Output => l_Output
);
Thanks for replying though!

[@AlexanderForsman]

If i wanted the inverted output on the instansiated version, how would i do that?

[@VHDLwhiz]

You can make a new signal with a concurrent assignment like this:
InvertedSig

[@AlexanderForsman]

@@VHDLwhiz i tried it, but the compiler complained that I couldn't use an output signal like that.

[@vhdlwhiz2]

@@AlexanderForsman Oh, OK. If you want to read an output within the module, you must create a new "shadow" copy of it which you use consistently within the module. Just a regular signal which you can read and drive. Then you assign to the output concurrently from the copy like this:
MyOutput

[@AlexanderForsman]

@@vhdlwhiz2 ok, thx. I'll try that.

[@Niko_Leben]

Great video!

[@TheStrelok7]

PERFECT!!!

[@zattiya]

you /should have picked a more complicated example to show such a basic concept.

[@rabomeister]

LMAO