Why casex/casez | Lets Learn Verilog with real-time Practice with Me | Day 17

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  • Опубліковано 11 січ 2025

КОМЕНТАРІ • 8

  • @S_R911
    @S_R911 Рік тому

    keep going bro ...Lots of love . I am not missing even a single video of yours...

  • @PilatesinSacramento
    @PilatesinSacramento Рік тому

    I'd second the comment below. It seems as though casez accounts for if an input is 'z' which is floating and 'x' would be broader which would account for 'z', 'x' or 1 or 0. In the exercise on HDLBits, there is nothing saying that an input could be floating. I'd assume that all 8 inputs are being driven to valid 1 or 0 values. Anyway, thank you for another great video. I'm moving along through them and enjoying it!

  • @nityanand4581
    @nityanand4581 Рік тому

    Please elaborate more on casex vs casez. i am confused after reading from lot of sources. Synthesis vs sim diff and why casez is better

  • @tanuraj1928
    @tanuraj1928 9 місяців тому

    I think msb bit should be taken as priority bit not lsb bit.
    Correct me if i am wrong

  • @nimmanashashankkrishna6114
    @nimmanashashankkrishna6114 6 місяців тому

    why is the hdl site not working

  • @ivogaycaramuti1243
    @ivogaycaramuti1243 7 місяців тому

    very useful video

  • @anandbvs143
    @anandbvs143 Рік тому

    Nice

  • @EE23M112MdAli
    @EE23M112MdAli 11 місяців тому

    a=0
    b=0