I hope you get invited to other channels that use this video in their content! LTT is probably too basic, but techtech potato, level one techs and some of the more tech heavy ones😊
Yeah, nun verstehe ich AMD, weshalb es den TDP Wert vo einigen Wochen so niedrig getrimmt hatte. In deinem Video hast du nur kurz über Temperatur geredet und vermutlich hatte dadurch AMD Angst bei höherer Taktung auf den CCD zu viel abwärme produziert wird und somit zum Totalausfall wird. Nach einpaar Wochen hatte sich die Angst via AMD als unbegründet herausgestellt. Ansonsten ein super Video und auch super erklärt. P.S. English is good - not very good. Hier fehlt ein wenig der Slang. 🙂
Having 2-layer 3D-cache makes sense given the rumors that the new X3D-CPU's can boost higher. More compact 3D-cache that is further away from the compute cores would be less sensitive to heat coming from the compute cores.
As the SRAM cache is now probably stacked now on multiple layers. Wondering if it suffers also from exes heat. Question is how much can you stack before heat dissipation starts to become issue and making it more unstable etc... Even SRAM is more efficient and generates less heat.
Wasn't the main issue with the clockspeeds the lower voltage tolerance of v-cache, not the heat? The heat issue is solved with lower power limit and lowered thermal limit, but it should have still been able to clock high for as long as it had the thermal headroom instead of having locked core voltage
@@shepardpolskaSaying new X3D chips could "clock higher" really just means in relation to the non-X3D configuration. Since zen5 effectively has the same freq limits as zen4 while generally being more efficient, it's very likely X3D will get closer to this because it'll have more headroom. Especially since X3D uses binned chips capable of running lower voltages.
Came back here immediately after hearing from GamerNexus that Zen 5 X3D might be flipping the cache & ccd. Potential great explanation for the differences you've discovered: If the cache is no longer on top, less circuitry needs to go through the silicon itself! 😊
@@Fin1nishingMoveConsumer tasks won't see Zen 5 gains. Zen5 gains more on Linux and more specialized tasks. Zen5 also gains efficiency compared to previous Zen4 release.
Double stacked 3D cache on both ccd's for 12c/24th and 16c/32th? I've also pondered Zen 5c for either mixed Z5+Z5c or all Z5c for up to 24/48. Idk if 5c cores can clock as high. But, my laymen guess is 5c's lower cache per core wouldn't be an issue with the double stacked 3D cache. I've also thought about chips like the 8700F getting 3D cache. Again, this is just me thinking aloud. But, I could see those defective APU's being repurposed into budget 3D options that would perform between standard 7700X/9700X and 7800X3D/9800X3D. Or, would the halved 16mb L3 on the die itself be too little?
This is kind of a part 2 to my first comment... What I'm getting at is how important is having a regular pool of L3 cache on the die directly attached to the cores versus just having the large 3D cache to compensate? I've heard people say that packing smaller (but equal ipc) Zen 5c cores in wouldn't hurt performance because of that large pool of 3D cache. That way you could have hybrid 20c/40th, or a 24c/48th all Zen 5c chip. Like I stated before, this is just me as a laymen asking if this would work. Idk if the clocks would have to be significantly lower on the 5c cores either. I do know that AMD has used hybrid Zen 4/4c in Phoenix APU's. And, when all cores ran at a fixed clock performance was the same.
The 35% reduction in L3$ is quite an amazing feat. Also, with the TSVs, this is another "generational" change, and I'm impressed with how far R&D goes to improve it unlike the IOD.
@@NootNoot. AMD would probably prefer staying with the same I/O die for an entire memory generation, but I think we will see at least minor a revision, as the current one caps out at 6000MT/s.
@@andersjjensen Zen6 leak show complete redesign I/0 die and 10x increase bandwidth to CCX and decrease latency, this is most liekly reason why we not see I/O changes now they simply focus all efforts on zen 6 i/o die
OK, you have managed to engage my interest for Zen 5. This is the kind of analysis I have been missing since Jim from @AdoredTV stopped making tech content. That and his "Awright, guys, how's it goin'?".
Gosh those super tight-in shots near the TSVs just blew my mind. Reminds me of just how exquisitely complex modern processors are, and of course it's a tour de force in macro photography.
Apparently the puzzle has been solved. The reason there's so few TSVs is because the V-Cache is underneath the CCD, so the CCD doesn't need power TSVs, just data.
AMD kept saying it was a redesign. Your video highlights this. It seems like most people can't see past minimal IPC uplift and the introduction of full avx512. Excited to see what 3Dvcache brings for this gen.
Yup. SO many comments about "AMD is getting lazy now" and what not, as if Zen 4 to Zen 5 was just Intel 13th gen to 14th gen. It can't just be that someone screwed up somewhere in this or that they just didn't get the results that they were expecting, it's always gotta be some stupid conspiracy about the chip manufacturers being Scrooge McDuck, doing everything they can not to have to make better chips. It's incredibly frustrating to try to have meaningful discussions in the tech community. These modern high performance processors are easily the most advanced pieces of bleeding edge tech that we have in our daily lives - and even enthusiasts take it for granted.
Most people don't understand that a major architecture redesign doesn't always improve performance significantly at first, there can even be performance regression in some aspects. But updating incrementally without a major rebuild eventually gets diminishing returns. So throwing everything in the air and rebuilding with a new floorplan allows large structures to change, this also increases the headroom for improvements later. Making a large structure change on an existing floorplan means working around existing structures and wasting transistors to work around stuff, squandering the transistors a new process node brought. Eventually things get complicated and your "low hanging fruit" updates are gone, like beefing up some execution units to increase FP or INT performance. Eventually you need a whole lot of stuff to change at once or you suffer bottleneck whack a mole. You need a more complex branch predictor to handle more throughout, beef up all the low level caches to handle that, completely redo the execution side to support 512 bit wide paths. Everything gets built bigger essentially. Zen 5 is fresh and should have lots of headroom to improve with future process nodes. There's lots of easy low hanging fruit that should bring easy large gains by simply beefing up a few components.
It took me a whole undergrad just to understand some terminologies present in video. "Just Understand". Semiconductor is quite interesting. Stuff like these make me realize there is so much more to explore. I hope more people find such stuff interesting. Hey UA-cam algorithm push this video. I hope "this" helps.
AMD like had extra SI vias for the previous generations to increase yields. Now that the process has matured, they don’t need them. The extra vias could have caused the power problems of the previous gens that restricted over clocking.
You are probably the most interesting tech researcher I have come across on the internet. I love how you take complex topics and break them down for people like me. It's truly valuable.
Bro, the images are bonkers. They look so good, even after zooming in that much. Thanks for the explanation of the chips, it makes the images even more amazing.
The fact AMD has found issues all over the place, and UA-camrs like HBU have as well indicates that something on the consumer PC end isn't capable of pushing Zen 5 to their potential.
@@HighYield Haha, c'mon, does a 'fan' get exclusive beautiful high-res die shots in private to make for a video? /s Anyways, great work! Although idk if it would make for a good video, and the question of attainability, I'd love to see Turin Dense die analysis. Zen5c has changes to it's CCX arrangement as well sharing L3$ unlike it being split like Zen2. And oh boy, are those CCDs looong, which kinda of makes Zen5c on desktop unlikely.
@@NootNoot. There are still a few project in work, for example a Nvidia GV100. I'd love more deep dives, but Fritzchens does whatever he wants to (and rightfully so).
this content is insane, the information we are getting here is so detailed and is about a product that is so new... I just can't believe it you guys are crazy :)
Amazing, like looking into the furthest depths of the universe. Beautifully presented and explained. Nice balance between highly technical and overview. More please!
The AMD has said that 3D cache version can clock closer to non cache version. So while 7000 and 9000 non cache versions have allmost same clockspeed… the 3D cache version 9000 version should clock higher than 7000 series does. And that is the main advantage this time.
Makes sense for binning purposes why there's no 800X non-3D CPU's anymore, especially for Zen 5 if the X3D can clock closer to non-3D. I suspect a 9700X3D will eventually surface that performs on par with the 7800X3D due to lower quality binning. AMD's naming convention gives them a lot of wiggle room for future Zen, with non-X, X, and X3D variants to fill in gaps if needed, or remove where redundant. I've been on the fence with Zen 5 X3D but these kind of deep dives give me hope that it'll finally be worth moving to AM5.
9000X3D will deliver a much bigger jump from 7000X3D than 9000 did from 7000. Massively higher clockspeeds is the reason. Less sensitive 3D cache = Higher clockspeeds.
I really do appreciate the invaluable work that goes into these videos. The only other people who go above and beyond for such a niche subject matter are Anandtech, who are now defunct, and Chips & Cheese. Thank you for your effort.
Amazing content! Scratchs the hitch of the cpu/gpu deep dives that only anandtech did. Hope your channel grows and that you keep posting this kind of content. Thank you ❤
- 00:00 🎥 Introduction to Zen 5 architecture and chip design, focusing on detailed die shots of Ryzen 9000 Zen 5 CPU. - 01:05 🔍 Zen 5 chiplet layout explained: classic Ryzen design with I/O-die and Core Complex Die (CCD) positioning. - 01:50 🟦 Zen 5 CCD now has a square shape compared to Zen 4’s rectangular one, yet similar in size. - 02:16 💡 Zen 5 packs 26.6% more transistors than Zen 4, leading to a significant increase in transistor density. - 02:45 🧑💻 Overview of the I/O-die: larger but with low transistor density due to analog circuits and interconnects. - 03:25 🧠 Memory interface features dual-channel DDR5 support with a 160-bit wide interface. - 04:11 🔗 Infinity Fabric interconnects connect CCDs with I/O-die, crucial for memory access. - 04:29 🎮 RDNA2-based iGPU with two compute units, offering basic GPU functionality. - 05:29 ⚙️ Zen 5 reuses the same I/O-die from Zen 4, a cost-effective decision since I/O remained state-of-the-art. - 06:34 🧩 Zen 5 CCD design features a unified L3 cache surrounded by eight CPU cores, with a more compact L3 cache layout. - 08:28 🔧 AMD achieved significant reductions in L3 cache area through tighter transistor packing and elimination of gaps. - 09:42 🏗️ TSVs (Through-Silicon Vias) in Zen 5 have undergone a major redesign, becoming smaller and fewer compared to previous generations. - 12:44 🔬 Zen 5’s TSVs measure as small as 3 by 3 micrometers, a drastic reduction from Zen 3 and Zen 4. - 14:29 🧊 Potential issues with heat dissipation arise if the same 3D V-Cache chiplet from Zen 4 were applied to Zen 5, due to differences in L3 cache size.
Incredible video, it's super interesting to see the details and thoughts and considerations that went in these chip designs, it's just fascinating to see...
Excellent explanation. I want to see how X3D cache will be implemented on Zen 5 since some reports tell that the 9950X3D and 9900X3D will bring something new.
You could also use project Lasso tied 2 games so that whenever you launch a game, it automatically disables The Other CCD for only that game process @@Dr.WhetFarts
@@Dr.WhetFartsif both CCDs have V Cache that means that process can stay in any CCD without worrying their data is in the other, they don't have to be specially allocated nor windows have to use core parking
@@reiniermoreno1653your trusting that windows scheduler will keep games on ccd0 and not spread the load to ccd1 (I am expecting Xbox game bar + amd driver core parking still be used as there is a massive latency penalty to keep the L3 in sync when a process moves onto another ccd) 9800x3d should still be preferred gaming cpu
Really like your videos. As someone who mostly works on the hardware language design level, it is interesting to see insight on the packaging and layout. Those layout guys have always felt like wizards, like hardcore tetris fitting everything in neatly.
@@HighYield Oh yes ;-). Please. UA-cam Video compression on itself is just bad at 1080p, convert a 1080p video to 4K 60FPS would already be great to improve quality on youtube. Thanks again for your videos and all the best
@@CalgarGTX I don't have UA-cam Premium and I watch 4k videos every day. Maybe you're thinking of the new "1080p premium" option for higher bitrate 1080p.
3D cache being double stack would make sense, they managed to reduce the connector sizes that much because they moved the logic gates from the CCD to the first layer of the 3D cache.
i just stumbled across your channel by pure luck.. didn't know we tech geeks can dive this deep into processors. you earned a new subscriber 🫡 hopefully alot more soon. EDIT: is it possible for us to download these images ?
I was just complaining the other day that I couldn't find deep dives into newer CPUs. This is far cry different from the AdoredTV I have missed since he left, but definitely scratches the itch. Also those die shot are really amazing! As far as the TSV question: I would like to throw out the cavet that I am not an engineer, but just based on your own comparison of Zen 3 to 4 to 5 fuels my guess to the mystery. When designing a new feature, to both improve on previous designs and not waste space created by other optimizations the TSVs that were added were "possibly" over-engineered, and given extra space to ensure the new feature would either work, or work after intense testing, and microcode optimization. As such the smaller TSVs are the result of them being tested and optimized. The overall structure/stability of the chiplet is not at risk, because any additional area that isn't filled in with other parts of the overall design would be filled in with inert martial. I don't have a reference to back that up, but it just makes sense to me. the overall package has to be kept as flat and structurally sound as possible to provide a solid contact for the soldering of the IHS. The Gamer's Nexus video of the AMD labs shows how they measure the "curvature" of the overall package once the dies are inlaid to ensure they are not exceeding those limits.
Great presentation! Technical enough to be widely understood. (I hope.) You should be on AMD’s marketing team. If the rumors about VCache overclocking are true, it makes sense that the VCache would be placed above the L3 cache, allowing for better cooling. It’s unfortunate this architecture doesn’t perform better in gaming. If the boost was closer to 8-10% instead of just 3-5%, I think gamers would have a much better opinion, and more people satisfied.
It's a fascinating question though: If clock-speeds are higher than with Zen4X3D, does that mean that the performance-improvement from X3D will actually be HIGHER? Since the Core-die doesn't have to clock down as much, that could mean that some of the negatives of X3D could be mitigated, and X3D-CPU's will henceforth be better for production-work and work which favours frequency over cache.
I could see the new 3D V-Cache extending over the entire die with the actual memory elements being a little spread out. This would allow for more thermal vias to assist in transferring heat from the CCD, through the V-Cache, and into the cooler. With the vias being so much smaller, thermal expansion resulting from the two dies being a different temperature will become a bigger issue. Improved heat transfer through the V-Cache will be required. Keeping the two dies the same temperature will be very important. It should also help in allowing the new parts to reach similar frequencies as the non-V-Cache versions. On a side note, using smaller vias could help in decreasing the power consumption when communicating over the cache bus. It could also help in maximizing the frequency. As far as the physical connection between the two dies goes, a reduced via count is a big issue. I assume additional structural vias would be present along the edge of the dies. Vias can take up a shocking amount of space compared to transistors. One really wants to avoid them as one typically has to compromise the logic in order to fit them in there. So reducing the number of logic / power vias to only what is required then moving the structural vias to the edge is probably the way to go. If looking for additional vias, that is where I would look.
This was such an insanely cool video. It would be awesome to have a chip designer come on and diacuss these images and reveal more of the mysteries of these chips. What a marvel of human engineering.
I was wondering if there'll be less 3D cache per CCD, but AMD will make up for it by populating both CCDs, rather than just one like in the current 3D v-cache.
The problem with marketing BS are for games. even with seeing review and the wider bunch of things and interview with Mike Clark(chief arch of zen), it was definitely designed for Core workload. It true AMD marketing teams are kind of stupid, but you still need something to show. and it makes me wonder if there a spy from nvidia pulling strings with stupid marketing (RDNA3 and delayed RDNA4) on GPU side
@@noobgamer4709 Seems to be a combination of Windows 11 being atrocious and AMD exaggerating their gains rather than just AMD being dumb. The differences between Windows 10 and Windows 11 in performance are massive especially on Zen 5, check out Tech Yes City's recent vids on it.
To be fair, what AMD engineers consider exciting may be different than consumers find exciting. I do think a smaller Vcache chiplet looks likely, but still be wary of taking such comments too out of proportion.
Another great content and amazing Die-shot. It's really interesting how these change in L3 cache will affect the next X3D implementation, Well I hope we don't have to wait too long. Btw I prefer this kind of content and I wish more people will get over gaming benchmark, gaming isn't everything.
@@maynardburger I can agree that gaming does get people interested in PC hardware, which X3D is that gaming first kind of product. But when I see review channel going on a rant about how bad zen5 gaming performance are, and ignore the efficiency and performance benefit it brings to other workload is like blaming a knife for not being a fork.
@@Sintrania It is not really about the performance itself though. It was about the performance claims made by AMD. Having relatively the same performance as last gen at much lower power is great! But they didn't advertise that... They advertise enormous gains that simply weren't there. People don't like being lied to. It is really that simple.
@@JustSomeDinosaurPerson and actually the performance claim is right, after they fix it with windows update and microcode update. It’s a bad PR not a bad product, they should have delay it’s release until they can get all of the aspects right. The review were ‘at the time of review’ with AMD messy guidelines, it’s no surprise the zen 5 launch is so bad. I’m not even an amd fan but It’s sad to see a good products label as a failure just because of a bad PR decision, I love the efficiency gain in multi core workloads and I can’t wait to compare it to Intel’s arrowlake.
Thanks for the video it was very interesting. I like to see the inner workings of what makes my pc work even though i have no idea what i'm looking at.
For me, the main thing that surprised me (after this video), is how much changed and yet how much AMD managed to stick to the performance of a refined and "aged" design. Whilst we all would love a 20% uplift after a redesign, Im personally very impressed we didn't see a more obvious drawback/regression like on MTL
AMD has long had an option in the AGESA called "X3D", for which the options are "Auto, Disable, 1 stack, 2 stacks, 4 stacks" so I would not be surprised by a 2-hi stack
INTERESTING...! Could you give a reference for this claim? Would be very interesting if you could show this info' to High Yield, and have him determine if there's any correlation to potential multi-stacking.
@@predabot__6778 It is found under AMD CBS/Zen Common Options/X3D. Some motherboards expose this menu, but not all. ASROCK usually has these exposed, but this is not really a menu made by the motherboard vendor, it is all from AGESA which they get from AMD. But they can just choose weather or not they want to expose all of the knobs from AMD to the user.
@@predabot__6778 Acording to more law is dead, RDNA3 MCDs could have V-cache stacked 2 chips high if I remember correctly, MCDs do seem to have vias for extra cache for at least 1 extra layer
@@predabot__6778 AMD is shifting from AGESA to open source firmware after ZEN5 so anyone will be able to see it. They have some experimental implementations already operating with Zen5. It will fit well with coreboot IIRC
It's no surprise they use more than one stack height, considering EPIC x3d chips had like a gigabyte of v-cache even in previous generation despite using the same CCD chiplets.
Amazing analysis of the pictures, great content I wonder what the perf would be if the 9800X3D came with 160MB (32 + 64 + 64) of L3 cache, would be super exciting if that was the case
Since the 9800x3D has been launched we know that the Stacked L3 is underneath. The TSVs are probably for a future product with a 2nd cache stacked on top too. Double stacked will be for gaming enthusiasts, Stacked cache will become the mainstream, while the entry level models will have the cache disabled.
I picture it’s engineers as gods that are designing large scale cities on an almost atomic scale. The channels and the roadways they need to build are incredibly complicated and small. It must be daunting. It would be cool to have a virtual reality tour to see what it would be like to zoom in and out of the three dimensions of the chip. To be a couple nanometers tall and to examine the miniature city built with light.
Great video. I watched it all and understood not a lot hehe. But I guess that's the learning curve that watching videos like offers. AMD did officially indicate that the Zen 5 X3D implementation will be reworked versus Zen 4 so it is quite interesting to see how this materialises. Perhaps the emphasis was on X3D all along? It could be marginally or markedly faster than the 7800X3D, so the future is very exciting. I will keep tuned for the X3D deep dive video to see what else I can fail to understand. 😅
I really expected a new I/O die with Zen 5, but the fact that it is the same perfectly explains why Zen 5 has the same difficulties with two memory sticks per channel as Zen 4.
And why the uplift of Zen 5 over Zen 4 is so small. Better cores that are as memory constrained as the previous gen which was already memory constrained...
It seems they're putting all their IO efforts into Zen6 but honestly I think it's unlikely we'll see significantly higher frequencies with 2+ DPC DDR5 as there are inherent signal integrity challenges that go beyond what is limited by the PHY and UMC. I'd expect an improvement but wouldn't be surprised if supported speeds still aren't significantly higher in these configurations.
@@JJFX- Maybe Zen5+ next year with the Zen 5 CCD but new IO Die? With all the AI hype they might accelerate some things. You're right though, we're clearly running into the limits of DIMMs, as for the first time in decades we're seeing new forms pop up like CAMM2.
@@MacGuyver85 Well I doubt there will be an iterative generation on desktop prior to Zen6. I see the most significant IO improvements going hand in hand with the advancements brought by Zen6. Even though Zen5 overhauled the core design, in some ways this generation can be viewed as Zen4++. The next generation will likely bring it all together as the pinnacle of AM5 prior to moving forward with DDR6.
Every time I watch one of your deep dives I am amazed that humanity is able to make such intricate pieces of technology. People hating online about how AMD sucks because Zen 5 doesn't increase gaming performance enough really have no clue about the insane engineering that goes into making chips.
I'm always amazed to see how the chip engineers manage to get the different parts of a chip arranged in such a way that the result is a rectangular shape, with little to no empty space in between as filler. I wonder how much time they have to spend just on the layouts
It is insane how he managed to do this. The higher ups must be watching this and devising all sorts of strategies to counter this technique from going mainstream.
The resolution of those die shots is actually insane
Insane die shots from an insanely talented person: Fritzchens Fritz 😎
@@HighYieldplease tell me the nickname is Fritz²
@@HighYielddoes he make content of how he's able to produce these images? I'd watch
Yeah, the resolution blew me away. The level of detail is something I thought only engineers at the likes of AMD/TSCM/Intel had access to.
@@HighYield Is this done with electron microscope?
It's a pity that this kind of deep-dive content has such a niche audience. Your channel deserves to be far bigger than it is.
I already have a much larger audience than I ever imagined. I'm pretty happy. Plus it's cool to have such a tight-knit community :)
Qualtity is just as important as quantity!
I hope you get invited to other channels that use this video in their content! LTT is probably too basic, but techtech potato, level one techs and some of the more tech heavy ones😊
Such is the enthusiast side of an already esoteric topic. I barely found this channel and am now subscribed!
nah, everything is ruined when it goes from niche to mainstream.
Such a nice channel! Wish I knew it earlier :D Great video!
Ein Kommentar vom 8auer, jetzt kann ich glücklich sterben ;) Dankeschön!
Verdientes Lob !
dercucker!
Yeah, nun verstehe ich AMD, weshalb es den TDP Wert vo einigen Wochen so niedrig getrimmt hatte. In deinem Video hast du nur kurz über Temperatur geredet und vermutlich hatte dadurch AMD Angst bei höherer Taktung auf den CCD zu viel abwärme produziert wird und somit zum Totalausfall wird. Nach einpaar Wochen hatte sich die Angst via AMD als unbegründet herausgestellt. Ansonsten ein super Video und auch super erklärt. P.S. English is good - not very good. Hier fehlt ein wenig der Slang. 🙂
Du musst echt den Kanal bingen. Lohnt sich.
Having 2-layer 3D-cache makes sense given the rumors that the new X3D-CPU's can boost higher. More compact 3D-cache that is further away from the compute cores would be less sensitive to heat coming from the compute cores.
As the SRAM cache is now probably stacked now on multiple layers. Wondering if it suffers also from exes heat. Question is how much can you stack before heat dissipation starts to become issue and making it more unstable etc... Even SRAM is more efficient and generates less heat.
Wasn't the main issue with the clockspeeds the lower voltage tolerance of v-cache, not the heat? The heat issue is solved with lower power limit and lowered thermal limit, but it should have still been able to clock high for as long as it had the thermal headroom instead of having locked core voltage
@@shepardpolskaSaying new X3D chips could "clock higher" really just means in relation to the non-X3D configuration. Since zen5 effectively has the same freq limits as zen4 while generally being more efficient, it's very likely X3D will get closer to this because it'll have more headroom. Especially since X3D uses binned chips capable of running lower voltages.
I don't understand. How would a higher stack the heat has to be dissipated through solve any heat issues?
@@unvergebeneid Heat comes more from the cores than from the cache. That's why they stack on the L2 cache in the first place.
Came back here immediately after hearing from GamerNexus that Zen 5 X3D might be flipping the cache & ccd. Potential great explanation for the differences you've discovered: If the cache is no longer on top, less circuitry needs to go through the silicon itself! 😊
Double stacked 3D cache?
Welcome back, consumer HBM
i havent looked at it like this but the more i think about the more i find it super funny xd
Welcome back, Zen 4 performance. Now called Zen 5.
@@Fin1nishingMoveConsumer tasks won't see Zen 5 gains. Zen5 gains more on Linux and more specialized tasks. Zen5 also gains efficiency compared to previous Zen4 release.
Double stacked 3D cache on both ccd's for 12c/24th and 16c/32th?
I've also pondered Zen 5c for either mixed Z5+Z5c or all Z5c for up to 24/48. Idk if 5c cores can clock as high. But, my laymen guess is 5c's lower cache per core wouldn't be an
issue with the double stacked 3D cache. I've also thought about chips like the 8700F getting 3D cache. Again, this is just me thinking aloud. But, I could see those defective APU's
being repurposed into budget 3D options that would perform between standard 7700X/9700X and 7800X3D/9800X3D. Or, would the halved 16mb L3 on the die itself be too little?
This is kind of a part 2 to my first comment... What I'm getting at is how important is having a regular pool of L3 cache on the die directly attached to the cores versus just having
the large 3D cache to compensate? I've heard people say that packing smaller (but equal ipc) Zen 5c cores in wouldn't hurt performance because of that large pool of 3D cache.
That way you could have hybrid 20c/40th, or a 24c/48th all Zen 5c chip. Like I stated before, this is just me as a laymen asking if this would work. Idk if the clocks would have to
be significantly lower on the 5c cores either. I do know that AMD has used hybrid Zen 4/4c in Phoenix APU's. And, when all cores ran at a fixed clock performance was the same.
The 35% reduction in L3$ is quite an amazing feat. Also, with the TSVs, this is another "generational" change, and I'm impressed with how far R&D goes to improve it unlike the IOD.
I think the lack of IOD improvement is kinda the point of the design lol
@@RyTrapp0 I don't disagree. When AMD has 3D V-cache for gaming, from their POV might as well save R&D until necessary.
@@NootNoot. AMD would probably prefer staying with the same I/O die for an entire memory generation, but I think we will see at least minor a revision, as the current one caps out at 6000MT/s.
@@andersjjensen Zen6 leak show complete redesign I/0 die and 10x increase bandwidth to CCX and decrease latency, this is most liekly reason why we not see I/O changes now they simply focus all efforts on zen 6 i/o die
OK, you have managed to engage my interest for Zen 5. This is the kind of analysis I have been missing since Jim from @AdoredTV stopped making tech content. That and his "Awright, guys, how's it goin'?".
yeah I miss him too
Same. I even began to understand the Scottish accent better thanks to him.
Jim is a great guy but he just wasn't built for the modern internet unfortunately.
I miss him too for sure
Miss his content, but totally get why he stopped. At least he helped really get this content niche off the ground for channels like this one.
Gosh those super tight-in shots near the TSVs just blew my mind. Reminds me of just how exquisitely complex modern processors are, and of course it's a tour de force in macro photography.
Apparently the puzzle has been solved. The reason there's so few TSVs is because the V-Cache is underneath the CCD, so the CCD doesn't need power TSVs, just data.
Right, the V-Cache is getting it's power through a shared power rail supplied by the package.
AMD kept saying it was a redesign. Your video highlights this. It seems like most people can't see past minimal IPC uplift and the introduction of full avx512. Excited to see what 3Dvcache brings for this gen.
Don’t forget the new branch predictor that can look 2 branches out instead of 1.
@@Fractal_32 Wait, that's insane 😮
@puilp0502 Check out the chips and cheese article on the topic, I tried supplying a link to the article but UA-cam did not like that comment.
Yup. SO many comments about "AMD is getting lazy now" and what not, as if Zen 4 to Zen 5 was just Intel 13th gen to 14th gen. It can't just be that someone screwed up somewhere in this or that they just didn't get the results that they were expecting, it's always gotta be some stupid conspiracy about the chip manufacturers being Scrooge McDuck, doing everything they can not to have to make better chips. It's incredibly frustrating to try to have meaningful discussions in the tech community.
These modern high performance processors are easily the most advanced pieces of bleeding edge tech that we have in our daily lives - and even enthusiasts take it for granted.
Most people don't understand that a major architecture redesign doesn't always improve performance significantly at first, there can even be performance regression in some aspects. But updating incrementally without a major rebuild eventually gets diminishing returns. So throwing everything in the air and rebuilding with a new floorplan allows large structures to change, this also increases the headroom for improvements later. Making a large structure change on an existing floorplan means working around existing structures and wasting transistors to work around stuff, squandering the transistors a new process node brought. Eventually things get complicated and your "low hanging fruit" updates are gone, like beefing up some execution units to increase FP or INT performance.
Eventually you need a whole lot of stuff to change at once or you suffer bottleneck whack a mole. You need a more complex branch predictor to handle more throughout, beef up all the low level caches to handle that, completely redo the execution side to support 512 bit wide paths. Everything gets built bigger essentially.
Zen 5 is fresh and should have lots of headroom to improve with future process nodes. There's lots of easy low hanging fruit that should bring easy large gains by simply beefing up a few components.
"I've inserted chapters so you can go straight to the sections that interest you." Never subbed so fast.
And watched the whole thing anyways 😂
It took me a whole undergrad just to understand some terminologies present in video. "Just Understand". Semiconductor is quite interesting. Stuff like these make me realize there is so much more to explore. I hope more people find such stuff interesting.
Hey UA-cam algorithm push this video. I hope "this" helps.
im currently studying EE as a junior wanting to go into semi conductors this video is absolutely mind boggling how cool it is
AMD like had extra SI vias for the previous generations to increase yields. Now that the process has matured, they don’t need them. The extra vias could have caused the power problems of the previous gens that restricted over clocking.
Interesting idea, it does make a lot of sense.
Yeah, removing redundancy coupled with some further improvements makes sense.
Great Video, Thank you ! Side note, at 7:19 you wrote Core 4 twice on the right, instead of Core 5 :)
BTW, your presentation is now top-notch and professional. You have grown tremendously.
You are probably the most interesting tech researcher I have come across on the internet. I love how you take complex topics and break them down for people like me. It's truly valuable.
Thanks for the great work!
And thank you for your generous donation!
+1 for stats
Thx for your work. I love topics about internals 🙂
Bro, the images are bonkers. They look so good, even after zooming in that much.
Thanks for the explanation of the chips, it makes the images even more amazing.
This needs many, many more views. The fact that the leaked figures show much more than 'Zen5%' over Zen 4, I think you are definitely onto something.
The fact AMD has found issues all over the place, and UA-camrs like HBU have as well indicates that something on the consumer PC end isn't capable of pushing Zen 5 to their potential.
@HighYield and @FritzchensFritz the impeccable duo!
Honestly, Fritz is the one with the talent here. I'm just his fan :D
@@HighYield Haha, c'mon, does a 'fan' get exclusive beautiful high-res die shots in private to make for a video? /s
Anyways, great work! Although idk if it would make for a good video, and the question of attainability, I'd love to see Turin Dense die analysis. Zen5c has changes to it's CCX arrangement as well sharing L3$ unlike it being split like Zen2. And oh boy, are those CCDs looong, which kinda of makes Zen5c on desktop unlikely.
@@NootNoot. There are still a few project in work, for example a Nvidia GV100. I'd love more deep dives, but Fritzchens does whatever he wants to (and rightfully so).
@@HighYield Excited for what comes next!
This die shot was exclusive to you? :0 I'd die (pun very intended) to get it@@HighYield
this content is insane, the information we are getting here is so detailed and is about a product that is so new... I just can't believe it
you guys are crazy :)
Awesome channel, surprised I had never seen it before! YT finally recommended something worthy! :-)
Amazing, like looking into the furthest depths of the universe. Beautifully presented and explained. Nice balance between highly technical and overview. More please!
Ok, I do not know how it was recommended to me but now I know that I needed it.
Thank you and subscribed.
You and @FritzchensFritz - you both are treasures.
Thank you both for this amazing analysis. Cheers!
Incredible video. Incredible die shots. Incredible design from AMD. Simply WOW! What a time to be alive
Great analysis as always. I hope that Zen 5 X3D brings a larger leap in gaming performance than regular Zen 5 did.
The AMD has said that 3D cache version can clock closer to non cache version. So while 7000 and 9000 non cache versions have allmost same clockspeed… the 3D cache version 9000 version should clock higher than 7000 series does. And that is the main advantage this time.
@@haukionkannel if all of this is true then the 9800 X3D will be worth the buy.
Makes sense for binning purposes why there's no 800X non-3D CPU's anymore, especially for Zen 5 if the X3D can clock closer to non-3D. I suspect a 9700X3D will eventually surface that performs on par with the 7800X3D due to lower quality binning. AMD's naming convention gives them a lot of wiggle room for future Zen, with non-X, X, and X3D variants to fill in gaps if needed, or remove where redundant. I've been on the fence with Zen 5 X3D but these kind of deep dives give me hope that it'll finally be worth moving to AM5.
9000X3D will deliver a much bigger jump from 7000X3D than 9000 did from 7000. Massively higher clockspeeds is the reason. Less sensitive 3D cache = Higher clockspeeds.
I really do appreciate the invaluable work that goes into these videos. The only other people who go above and beyond for such a niche subject matter are Anandtech, who are now defunct, and Chips & Cheese. Thank you for your effort.
Didn't know about Chips & Cheese. Thx mate.
Amazing content! Scratchs the hitch of the cpu/gpu deep dives that only anandtech did.
Hope your channel grows and that you keep posting this kind of content.
Thank you ❤
- 00:00 🎥 Introduction to Zen 5 architecture and chip design, focusing on detailed die shots of Ryzen 9000 Zen 5 CPU.
- 01:05 🔍 Zen 5 chiplet layout explained: classic Ryzen design with I/O-die and Core Complex Die (CCD) positioning.
- 01:50 🟦 Zen 5 CCD now has a square shape compared to Zen 4’s rectangular one, yet similar in size.
- 02:16 💡 Zen 5 packs 26.6% more transistors than Zen 4, leading to a significant increase in transistor density.
- 02:45 🧑💻 Overview of the I/O-die: larger but with low transistor density due to analog circuits and interconnects.
- 03:25 🧠 Memory interface features dual-channel DDR5 support with a 160-bit wide interface.
- 04:11 🔗 Infinity Fabric interconnects connect CCDs with I/O-die, crucial for memory access.
- 04:29 🎮 RDNA2-based iGPU with two compute units, offering basic GPU functionality.
- 05:29 ⚙️ Zen 5 reuses the same I/O-die from Zen 4, a cost-effective decision since I/O remained state-of-the-art.
- 06:34 🧩 Zen 5 CCD design features a unified L3 cache surrounded by eight CPU cores, with a more compact L3 cache layout.
- 08:28 🔧 AMD achieved significant reductions in L3 cache area through tighter transistor packing and elimination of gaps.
- 09:42 🏗️ TSVs (Through-Silicon Vias) in Zen 5 have undergone a major redesign, becoming smaller and fewer compared to previous generations.
- 12:44 🔬 Zen 5’s TSVs measure as small as 3 by 3 micrometers, a drastic reduction from Zen 3 and Zen 4.
- 14:29 🧊 Potential issues with heat dissipation arise if the same 3D V-Cache chiplet from Zen 4 were applied to Zen 5, due to differences in L3 cache size.
Thank you for the work you do, it helps solidify thoughts of these products by knowing the physical characteristics.
Incredible video, it's super interesting to see the details and thoughts and considerations that went in these chip designs, it's just fascinating to see...
Thanks for the video. Always looking forward to new content from you!
Excellent explanation. I want to see how X3D cache will be implemented on Zen 5 since some reports tell that the 9950X3D and 9900X3D will bring something new.
Yes the 2 CCD parts will both have stacked cache
Only buy dual CCD if you actually needs the CPU power for applications, because in games, 9800X3D will beat them. Single CCD = No latency issues.
You could also use project Lasso tied 2 games so that whenever you launch a game, it automatically disables The Other CCD for only that game process @@Dr.WhetFarts
@@Dr.WhetFartsif both CCDs have V Cache that means that process can stay in any CCD without worrying their data is in the other, they don't have to be specially allocated nor windows have to use core parking
@@reiniermoreno1653your trusting that windows scheduler will keep games on ccd0 and not spread the load to ccd1 (I am expecting Xbox game bar + amd driver core parking still be used as there is a massive latency penalty to keep the L3 in sync when a process moves onto another ccd) 9800x3d should still be preferred gaming cpu
amazing works
OMG
those die shots are incredible
Wow, absolutely stunning photos and fascinating breakdown. Very informative.
may your channel explode. Thank you sir
That's amazing! Thanks for these inspections.
Really like your videos. As someone who mostly works on the hardware language design level, it is interesting to see insight on the packaging and layout. Those layout guys have always felt like wizards, like hardcore tetris fitting everything in neatly.
I am so dumbstruck by the quality and resolution of those images, salutations to the legend himself Fritzchens Fritz!
OMG THANKS SO MUCH for this video!!
Excellent video, as usual. THX!
This is just awesome. I literally could watch hours long videos of all this silicon pr0n further zoomed in.
I need to start doing 4K.
@@HighYield Oh yes ;-). Please. UA-cam Video compression on itself is just bad at 1080p, convert a 1080p video to 4K 60FPS would already be great to improve quality on youtube. Thanks again for your videos and all the best
@@HighYield Could be wrong but I think even the 1440p youtube res has double the bitrate of the 1080p. And 4k is locked to youtube premium these days
@@CalgarGTX I don't have UA-cam Premium and I watch 4k videos every day. Maybe you're thinking of the new "1080p premium" option for higher bitrate 1080p.
Love your work! and Fritz of course
😲
LOVE THIS VIDEO! THANK YOU!
Fritzchens photography is excellent
3D cache being double stack would make sense, they managed to reduce the connector sizes that much because they moved the logic gates from the CCD to the first layer of the 3D cache.
i just stumbled across your channel by pure luck..
didn't know we tech geeks can dive this deep into processors.
you earned a new subscriber 🫡
hopefully alot more soon.
EDIT:
is it possible for us to download these images ?
You can download them here: www.flickr.com/photos/130561288@N04/albums/72177720320942793/
This is insane.... Thank you sir!!!
Damn! You couldn't be more on the ball as it turns out
Just looked on the wrong side 🫣
I was always intrested on how these complicated processors.
I find your channel after 20+ years!🎉
Amazing video! TY 👍
I was just complaining the other day that I couldn't find deep dives into newer CPUs. This is far cry different from the AdoredTV I have missed since he left, but definitely scratches the itch. Also those die shot are really amazing!
As far as the TSV question: I would like to throw out the cavet that I am not an engineer, but just based on your own comparison of Zen 3 to 4 to 5 fuels my guess to the mystery. When designing a new feature, to both improve on previous designs and not waste space created by other optimizations the TSVs that were added were "possibly" over-engineered, and given extra space to ensure the new feature would either work, or work after intense testing, and microcode optimization. As such the smaller TSVs are the result of them being tested and optimized. The overall structure/stability of the chiplet is not at risk, because any additional area that isn't filled in with other parts of the overall design would be filled in with inert martial.
I don't have a reference to back that up, but it just makes sense to me. the overall package has to be kept as flat and structurally sound as possible to provide a solid contact for the soldering of the IHS. The Gamer's Nexus video of the AMD labs shows how they measure the "curvature" of the overall package once the dies are inlaid to ensure they are not exceeding those limits.
Great videos! Back in the days, Anandtech would have a few dense articles on architecture design.
It's nice to have this with channel.
Zen 4:
L3D
-----
CCD
Zen 5:
CCD
----
L3D
Your videos keep getting better and better
Very cool dieshots. Pictures like these makes me think that we are underpaying so much for this engineering marvel.
Great presentation! Technical enough to be widely understood. (I hope.) You should be on AMD’s marketing team.
If the rumors about VCache overclocking are true, it makes sense that the VCache would be placed above the L3 cache, allowing for better cooling.
It’s unfortunate this architecture doesn’t perform better in gaming. If the boost was closer to 8-10% instead of just 3-5%, I think gamers would have a much better opinion, and more people satisfied.
It's a fascinating question though: If clock-speeds are higher than with Zen4X3D, does that mean that the performance-improvement from X3D will actually be HIGHER? Since the Core-die doesn't have to clock down as much, that could mean that some of the negatives of X3D could be mitigated, and X3D-CPU's will henceforth be better for production-work and work which favours frequency over cache.
@@predabot__6778 That's the hope.
@@predabot__6778That means bad core parking wouldn't be as penalising as before then?
Very well done video. Thanks for sharing!!
I could see the new 3D V-Cache extending over the entire die with the actual memory elements being a little spread out. This would allow for more thermal vias to assist in transferring heat from the CCD, through the V-Cache, and into the cooler. With the vias being so much smaller, thermal expansion resulting from the two dies being a different temperature will become a bigger issue. Improved heat transfer through the V-Cache will be required. Keeping the two dies the same temperature will be very important. It should also help in allowing the new parts to reach similar frequencies as the non-V-Cache versions.
On a side note, using smaller vias could help in decreasing the power consumption when communicating over the cache bus. It could also help in maximizing the frequency.
As far as the physical connection between the two dies goes, a reduced via count is a big issue. I assume additional structural vias would be present along the edge of the dies. Vias can take up a shocking amount of space compared to transistors. One really wants to avoid them as one typically has to compromise the logic in order to fit them in there. So reducing the number of logic / power vias to only what is required then moving the structural vias to the edge is probably the way to go. If looking for additional vias, that is where I would look.
Great job! I wonder how much, if any, extra performance will they be able to get out of this new architecture as software catches up.
With those high res pictures, I would have loved for this video to be in 4k. Aside from that, great content!
This was such an insanely cool video. It would be awesome to have a chip designer come on and diacuss these images and reveal more of the mysteries of these chips. What a marvel of human engineering.
Also I really hope we get the die shot treatment for Lunar Lake, as I think Intel is finally innovating and making really interesting CPUs.
AMD has promised "exciting changes" to the x3d chips, and the die shots seem to show that there really is more than just marketing BS happening
I was wondering if there'll be less 3D cache per CCD, but AMD will make up for it by populating both CCDs, rather than just one like in the current 3D v-cache.
The problem with marketing BS are for games. even with seeing review and the wider bunch of things and interview with Mike Clark(chief arch of zen), it was definitely designed for Core workload. It true AMD marketing teams are kind of stupid, but you still need something to show. and it makes me wonder if there a spy from nvidia pulling strings with stupid marketing (RDNA3 and delayed RDNA4) on GPU side
@@noobgamer4709
Seems to be a combination of Windows 11 being atrocious and AMD exaggerating their gains rather than just AMD being dumb.
The differences between Windows 10 and Windows 11 in performance are massive especially on Zen 5, check out Tech Yes City's recent vids on it.
To be fair, what AMD engineers consider exciting may be different than consumers find exciting. I do think a smaller Vcache chiplet looks likely, but still be wary of taking such comments too out of proportion.
Another great content and amazing Die-shot. It's really interesting how these change in L3 cache will affect the next X3D implementation, Well I hope we don't have to wait too long.
Btw I prefer this kind of content and I wish more people will get over gaming benchmark, gaming isn't everything.
Gaming is like the main reason consumers care about X3D parts, though.
@@maynardburger I can agree that gaming does get people interested in PC hardware, which X3D is that gaming first kind of product. But when I see review channel going on a rant about how bad zen5 gaming performance are, and ignore the efficiency and performance benefit it brings to other workload is like blaming a knife for not being a fork.
@@Sintrania It is not really about the performance itself though. It was about the performance claims made by AMD. Having relatively the same performance as last gen at much lower power is great! But they didn't advertise that... They advertise enormous gains that simply weren't there. People don't like being lied to. It is really that simple.
@@JustSomeDinosaurPerson and actually the performance claim is right, after they fix it with windows update and microcode update. It’s a bad PR not a bad product, they should have delay it’s release until they can get all of the aspects right. The review were ‘at the time of review’ with AMD messy guidelines, it’s no surprise the zen 5 launch is so bad.
I’m not even an amd fan but It’s sad to see a good products label as a failure just because of a bad PR decision, I love the efficiency gain in multi core workloads and I can’t wait to compare it to Intel’s arrowlake.
Wow, simple and clear, love it!!
Thank you. This is fantastic!
Great review! Really interested to see 9800X3D announcement now! Planning a CPU/Mobo upgrade and will very likely buy it ASAP!
Thanks for the video it was very interesting. I like to see the inner workings of what makes my pc work even though i have no idea what i'm looking at.
My current Ryzen processor is from 2018, and I'm still happy with it 😊
The editing and explanation. Man hope you're going 1 million.
Love the effort and concept in the video. Thank you
Wow, UA-cam schlägt diese Video vor... damit hätte ich nicht gerechnet.
Fix ein Abo verdient!
Nice breakdown. Would LOVE to see something similar for the Threadripper or Epyc, or Intel's Xeon cpu's.
Super Arbeit. Danke für das tolle Video. Eine deutsche Version wäre natürlich der Hammer.
For me, the main thing that surprised me (after this video), is how much changed and yet how much AMD managed to stick to the performance of a refined and "aged" design.
Whilst we all would love a 20% uplift after a redesign, Im personally very impressed we didn't see a more obvious drawback/regression like on MTL
AMD has long had an option in the AGESA called "X3D", for which the options are "Auto, Disable, 1 stack, 2 stacks, 4 stacks" so I would not be surprised by a 2-hi stack
INTERESTING...! Could you give a reference for this claim? Would be very interesting if you could show this info' to High Yield, and have him determine if there's any correlation to potential multi-stacking.
@@predabot__6778 It is found under AMD CBS/Zen Common Options/X3D. Some motherboards expose this menu, but not all. ASROCK usually has these exposed, but this is not really a menu made by the motherboard vendor, it is all from AGESA which they get from AMD. But they can just choose weather or not they want to expose all of the knobs from AMD to the user.
@@predabot__6778 Acording to more law is dead, RDNA3 MCDs could have V-cache stacked 2 chips high if I remember correctly, MCDs do seem to have vias for extra cache for at least 1 extra layer
@@predabot__6778 AMD is shifting from AGESA to open source firmware after ZEN5 so anyone will be able to see it. They have some experimental implementations already operating with Zen5. It will fit well with coreboot IIRC
It's no surprise they use more than one stack height, considering EPIC x3d chips had like a gigabyte of v-cache even in previous generation despite using the same CCD chiplets.
Oh, finally. I was waiting for high-res pictures of Zen 5.
Thanks for the beautiful analysis :3
Amazing analysis of the pictures, great content
I wonder what the perf would be if the 9800X3D came with 160MB (32 + 64 + 64) of L3 cache, would be super exciting if that was the case
Since the 9800x3D has been launched we know that the Stacked L3 is underneath. The TSVs are probably for a future product with a 2nd cache stacked on top too. Double stacked will be for gaming enthusiasts, Stacked cache will become the mainstream, while the entry level models will have the cache disabled.
I picture it’s engineers as gods that are designing large scale cities on an almost atomic scale. The channels and the roadways they need to build are incredibly complicated and small. It must be daunting. It would be cool to have a virtual reality tour to see what it would be like to zoom in and out of the three dimensions of the chip. To be a couple nanometers tall and to examine the miniature city built with light.
Great video. I watched it all and understood not a lot hehe. But I guess that's the learning curve that watching videos like offers. AMD did officially indicate that the Zen 5 X3D implementation will be reworked versus Zen 4 so it is quite interesting to see how this materialises. Perhaps the emphasis was on X3D all along? It could be marginally or markedly faster than the 7800X3D, so the future is very exciting. I will keep tuned for the X3D deep dive video to see what else I can fail to understand. 😅
Your voice is very ASMR. Also, this deep dive into ZEN 5 is very interesting and informative.
godlike video man
I really expected a new I/O die with Zen 5, but the fact that it is the same perfectly explains why Zen 5 has the same difficulties with two memory sticks per channel as Zen 4.
And why the uplift of Zen 5 over Zen 4 is so small.
Better cores that are as memory constrained as the previous gen which was already memory constrained...
It seems they're putting all their IO efforts into Zen6 but honestly I think it's unlikely we'll see significantly higher frequencies with 2+ DPC DDR5 as there are inherent signal integrity challenges that go beyond what is limited by the PHY and UMC. I'd expect an improvement but wouldn't be surprised if supported speeds still aren't significantly higher in these configurations.
@@JJFX- Maybe Zen5+ next year with the Zen 5 CCD but new IO Die? With all the AI hype they might accelerate some things.
You're right though, we're clearly running into the limits of DIMMs, as for the first time in decades we're seeing new forms pop up like CAMM2.
@@MacGuyver85 Well I doubt there will be an iterative generation on desktop prior to Zen6. I see the most significant IO improvements going hand in hand with the advancements brought by Zen6. Even though Zen5 overhauled the core design, in some ways this generation can be viewed as Zen4++. The next generation will likely bring it all together as the pinnacle of AM5 prior to moving forward with DDR6.
I think zen6 will be on a new socket with ddr6 and pcie 6
Great content, as always.
Every time I watch one of your deep dives I am amazed that humanity is able to make such intricate pieces of technology. People hating online about how AMD sucks because Zen 5 doesn't increase gaming performance enough really have no clue about the insane engineering that goes into making chips.
usb3 and DP are connected in the same cluster to allow for DP alt mode and thunderbolt emulation, I believe.
Well done! Maybe we will see a A-synchronous Chiplet Design again when AMD can use two extra layers of 3D-VCache on one Die....
What an audio upgrade!!!
Can't wait for a full indepth Lion Cove and Skymont analysis when ARL comes out!
I'm always amazed to see how the chip engineers manage to get the different parts of a chip arranged in such a way that the result is a rectangular shape, with little to no empty space in between as filler. I wonder how much time they have to spend just on the layouts
Excellent work. This is brain candy for my nerd interests. Keep it up
It is insane how he managed to do this. The higher ups must be watching this and devising all sorts of strategies to counter this technique from going mainstream.
Thank you very much for this content!
I'm so gratefull.
Thanks a lot for this deep dive 😉👍
This video my god. Incredible work man needs 5 million views not 50k