Panelizing PCBs with Eagle CAD
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- Опубліковано 27 тра 2018
- Video about panelizing PCBs using Eagle CAD. I created a heavily modified version of Array ULP, which is now significantly more friendly.
New UPL can be found here:
github.com/cyberreefguru/Pane...
Music by www.bensound.com/
Don't forget to subscribe and give the video a thumbs up! - Наука та технологія
I didn't see the array ulp, in my ulp list
Looks like they removed it in the latest updates. More importantly, the most recent updates broke the ULP anyway. I've been trying to get it fixed but I'm having limited success. Sorry.
Awesome. Going to give this a try.
Thank you and your colleagues for creating these scripts, and thank you for this excellent overview of the method. Today I successfully used your script to panelize a simple audio amp design and everything worked great.
Thanks for the feedback. I am glad they are still working. Thanks for watching!
Excellent! Was really struggling to do it manually the other day, and thought to myself that there must be a better way. In my case I actually want to have a common (shared) GND and VCC for all the boards, since that would make it easier to test the panel as a whole.
You have a couple options for manually making a panel if you want to share signals. But this script creates a real editable board so you can connect anything you want. Glad you like the videos - don't forget to subscribe if you want to see more :)
This looks like surface mount LEDs; if you plan on soldering them to it could you show how it is done?
I'm pretty sure I posted a video a few years ago on solder SMDs. Let me check - if not I know I have raw video and pictures that I can turn into one.
Hi, how do you cut the individual boards afterwards? I can make panels of my designs but I haven't figured a way to serrate the board around each design. When I preview the gerber files it's just a solid board. Thanks:)
Takis - generally the board fab house cuts the boards using the board outline specified in the gerber files. If you don't have one, then the script might be skilling the outline because it is turned off, or on the wrong layer. Hope this helps.
@@cyberreefguru Thanks! I believe you mean the yellow dimenison layer #20?They cut around that regardless of panelizing?
I've ordered quite a few individual PCBs from JLCPCB but never a panelized version. I thought I needed some mouse bites or a v-score around each and every dimension rectangle after panelizing.I'll make a test order to see how they handle it.
@@p8051a yes, layer 20 I think (color is configurable). I think you need to ask them to panelize or you will just get one panel. Then I use a band saw to separate them if the design is relatively simple, or a CNC if the design is complex (if you have one).
@@cyberreefguru Thanks! I'll ask the fab and do accordingly. Keep up the good work. Always great info on your channel!
is there a way how to create the array from single PCB , so if I move LED1 for example, all LED1 in the view will be moved automatically too? ....similar function to 'Array or Block in Autocad'....changing 1 thing will do the change on all 'copies'
Jozef - I do not believe Eagle has that capability -- at least in in the PCB designer. It does now exist on the schematic side, so I imagine it is only a matter of time. Thanks for watching!
Thanks for this great work. When I run the ULP the Approx Board size is 0.00, 0.00. it's like it does not see the BRD.
Hi Waldo - do you have an outline on the dimension layer?
@@cyberreefguru Exactly what was happening. Thank you. Your script works!
I guess I spoke too soon. When I tried this again on a different computer I am getting" Footprint not found: E3,5-10@adafruit". There are multiple such errors leaving half populated boards.
Another new user error on my part. all's good now! Thanks again.
Hey @Waldo Mack - did you get everything worked out? Sounds like the original part library was not available when you ran the script?
Is that new board that you ran the exported script in still linked to the Schematic and BOM for the PCB design?
I don't think so -- it has components not defined in the schematic. Thanks for watching!
@@cyberreefguru Hmmmm I wonder how that would work then if one wants SMD assembly services as well.
@@briandodds assembly will be based on your Gerber files. The chip designators should not change on silkscreen so the BOM should match.
When I run the script, it asks which library it should use for there are muliple libraries with the same name (albeit in different directories). When I select the correct library, I would like it to remember that choice for the remaining copies of the design. But it doesn't do that. It keeps asking me for every instance of the design again which library to use.
Since most of the time my board dimensions are metric, it would be an advantage to express the origin and spacing in mm i.s.o. mil, or at least to have the option to choose metric i.s.o. imperial dimensions.
Error "Invalid wire width". This may be a ULP quirk. My VCC signal line was named "+5". This seems to cause an issue as it now considers this to be the wire width in the PCB design. When I rename the "+5" signal to "VCC" (or anything else that starts with an alphabetic character), the problem goes asway.
The script adds row and column numbers to the original component names (e.g. R2 becoms R2X11, R2X21, R2X31, etc.). I selected tValues and bValues for the text layers in the ULP, but in your UA-cam video you mentioned that it doesn't matter. And in fact, it doesn't because I get the same result if I choose another layer for the text. BTW, I don't have a _text layer. Even if I create those "underscored" layers, they don't show up in the selection list of the array ULP.
I get a whole bunch of DRC errors on the completed panelized board (overlaps and unconnected wires). The original disign had no errors at all.
I selected a value for Spacing wich is just a tad more than the size of the original board. But my polygons for the copper fill are just a bit bigger than the board outline, which may be causing this issue. I could make the spacing a bit more, but my board house (JLCPCB) recommends to have 0 space between the boards for the V-cut.
Any suggestions? I'm using Eagle version 9.5.2 (free).
Let me look into it. They have been making a lot of changes over the last 12 months.
Thanks. Meanwhile I sorted out most of the issues.
I missed the part where you mentioned that you ran the original panelize.ulp before starting the one you describe here. My bad ... If you make an update to your vlog, maybe you can be more explicit about it.
The dimensions are derived from the grid setting on the board. Problem solved.
The issue with the wire width is indeed related to the text in the component name. No worries.
The problem with the names (R2X11 etc.) is related to the fact that I didn't run the initial panelize.ulp. Would be a good idea to integrate that ulp in the array ulp. The name "panelize.ulp" is misleading as it doesn't do any panelizing at all ;-).
The DRC errors are gone when I adjust my copper pour polygons and put the boards far enough apart.
I started to dig in the ulp code with the aim to define the gap between the boards (as usually defined by the board house) i.s.o. manually adjusting the board size and to implement minimum and maximum panel sizes (as dictated by the board house) and have the ulp calculate automatically how many boards will fit on a panel. Still struggling with the behaviour of the dialog boxes in the ulp, but we'll get there...
Excellent news. I think I posted the code on GitHub so if you want to fork it and push changes please do so. Unless you’ve already done that - I’ll check this evening.
@@cyberreefguru,
Will do. I noticed that John Plocher already forked it to github.com/plocher/EagleTools/blob/master/ulp/make-panel.ulp. He cleaned up the code and added a few features (like looking for Milling lines if there is no board outline using Dimension lines. But it needs extra work. His V-score lines always start at origin (0,0), even when the source design is offset from the origin. And the panelizing feature only works for rectangular outlines. It will take a little while to get a finished ulp. I'll send you the code when I'm done, so you can torture it a bit ;-).
Has anyone been able to alter this for fusion ULP? I have tried changing s.polygons to s.polyPours...
I worked on it about a year ago but was not able to get it to work properly. If I have time I will try again. I was hoping someone at Autodesk would keep the ULPs up to date but no such luck.
would greatly appreciate!
@@cyberreefguru
Seems like the ulp doesn't work in the current version of Eagle !
Hi - I tested it with the new version of Eagle just 2 weeks ago and it worked fine (for me). It does not work properly in Fusion 360 though - I'm working to get it fixed. Can you provide more specific details or open a DR in Git?
I ran your script. Everything worked as was shown in the video but at the end when i viewed it using online altium gerber viewer and uploaded my board file, it is only showing outline on one board of the penal. I have replicated the board using your script to 12 times. But outline is only showing on 1 board. The previous script "spark fun penalizer" I had been running had the same problem.
Mohib - Autodesk changed the API about 12 months ago and broken a lot of the ULP scripts, mine included. I have not been able to get it working properly since. It makes a difference if you run it from Fusion 360 or Eagle -- the Eagle was working and Fusion was not. If you can't get it working in Eagle, then both might be broken now.
I added auto-V-Score annotation in the milling layer (and more) - see git@github.com:plocher/PanelizeArray.git, feel free to merge back if you are interested. Thanks for the inspiration!
Hi John - thanks for checking out the video and the code. I'll definitely merge it back as soon as I get a chance!
Hi Jackie!
Not Jackie, but I'll say hi! :)
No mousebites, no vgroove, nothing more than other copy-paste howtos I've seen. I just wasted ten minutes of my life.
Hello Rob - I'm not sure I understand your comment. The script should copy all the features of the board. I can see vgrooves being a problem because they are not on a copper or drill layer. Feel free to edit the script and issue a PR so the script meets your needs. Thanks for watching!
Vgrooves are used to allow the easy breaking-apart of the board. Some PCB fab houses support those. Others, that support milling but not Vgrooves you can space boards apart by maybe 5mm and have these little break-off chunks left (drilled along the board edge to create break-along perforations) to hold the boards together. Those chunks are called "mousebites." I've found a software that panelizes gerbers, from ThisIsNotRocketScience, but it doesn't panelize the PnP file. It's also amazingly crashy, so save your work often. Anyway, point-of-fact, that software leaves you hoping your PnP software supports the kind of panelizing that you want to do, which really leaves you (in most cases) with a grid of the same board. Hence I'm digging for ways to panelize in Eagle, and I'm looking for more than "you copy and paste it a bunch of times. Oh, and here's a trick to deal with names."
@@robstoddard9521 i have the same issue right now. Jlcpcb just won't accept the panelizing everyone show here on youtube or even search.