UVM Phases(Build_phase to Final_phase).

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  • Опубліковано 17 січ 2025

КОМЕНТАРІ • 11

  • @kaverih6611
    @kaverih6611 Місяць тому

    Thank you its more helpful🙌

  • @mohammadyusuf4192
    @mohammadyusuf4192 2 роки тому +1

    great deliver session

  • @5minutesclass188
    @5minutesclass188 2 роки тому +2

    Best UVM contents on youtube . thanks for that much effort to explain from scratch

  • @hknnkh6227
    @hknnkh6227 3 роки тому +2

    Such a great educative video. Your channel also rich, maybe you think to create playlist or improve them.

  • @vishalgowtham896
    @vishalgowtham896 5 місяців тому +1

    very useful and easily explained . Than you Ahmed sir,
    one doubt ---Is phases are written for every component ??

  • @Carlosramirez-he4zi
    @Carlosramirez-he4zi Рік тому

    thnx

  • @rahulkatike6837
    @rahulkatike6837 2 роки тому +1

    nice explanation, keep doing these kind of videos and can you please explain Synchronous FIFO complete testbench in UVM????

  • @suchitrajaee8379
    @suchitrajaee8379 2 роки тому +1

    Sir can you make video on how to make, make file to run code automatically

  • @mornemorkel1483
    @mornemorkel1483 3 роки тому

    I am trying to print topology same way you mentioned. However, it's not printing topology. Can you please help? Why it's not working?