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Munsif M. Ahmad
India
Приєднався 20 гру 2016
Welcome to our channel, where aspiring VLSI Front-end designers and verification engineers find their ultimate resource for knowledge and growth!
🎓 If you're a student or fresher in the VLSI field, this channel is tailor-made for you! 🎓
Join us on a captivating learning journey focused on two core pillars: Digital Logic Design and Verification. Through an in-depth exploration of fundamental concepts like Verilog HDL, System Verilog HDL as well as HVL, and SV-UVM (Universal Verification Methodology) our main goal is to equip you with the skills and knowledge needed to excel in VLSI Front-end Design & Verification.
🐍 As a bonus, we present pyuvm (python implementation of the UVM using cocotb), where we merge the versatility of Python with the potency of cocotb (COroutine based COsimulation TestBench), revolutionizing the verification ecosystem with innovation and elegance. Witness the fusion of two incredible worlds and expand your horizons beyond traditional boundaries.
Verilog FAQ's, verilog code for posedge detector & implementation of latch using 2x1 mux.
This video is all about how to write verilog code for posedge detector & how to implementation of latch using 2x1 mux.
EDA Playground link:- edaplayground.com/x/Zqsj
Digital electronics FAQ's Playlist:- ua-cam.com/play/PLDAnhhk0KczzR5FYjRgiJ4PZgCJcMmc_p.html
Verilog FAQ's Playlist:- ua-cam.com/play/PLDAnhhk0Kczy_KV4L_i9oiNTDzF7NQNWv.html
#semiconductor #vlsi #verilog #faq #interviewquestion #electronicengineering #veriloghdl #multiplexer #latch #posedgedetector
EDA Playground link:- edaplayground.com/x/Zqsj
Digital electronics FAQ's Playlist:- ua-cam.com/play/PLDAnhhk0KczzR5FYjRgiJ4PZgCJcMmc_p.html
Verilog FAQ's Playlist:- ua-cam.com/play/PLDAnhhk0Kczy_KV4L_i9oiNTDzF7NQNWv.html
#semiconductor #vlsi #verilog #faq #interviewquestion #electronicengineering #veriloghdl #multiplexer #latch #posedgedetector
Переглядів: 261
Відео
Verilog FAQ's, clock generation in Verilog, abstraction levels, full adder using 2 half adder.
Переглядів 2568 місяців тому
This video is all about Verilog HDL FAQ's // Q1) 5 different way's to generate clock in Verilog ? // Q2) Explain different abstraction levels, Implement full adder using 2 half adder ? EDA Playground link:- edaplayground.com/x/mtEY Verilog FAQ's Playlist:- ua-cam.com/play/PLDAnhhk0Kczy_KV4L_i9oiNTDzF7NQNWv.html Digital Electronics Playlist:- ua-cam.com/play/PLDAnhhk0KczzR5FYjRgiJ4PZgCJcMmc_p.ht...
Repetition Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #07
Переглядів 2,5 тис.Рік тому
This video is all about the introduction to Repetition Operators (Consecutive & Non-Consecutive) with respect to SVA (System Verilog Assertions). EDA Playground Link:- edaplayground.com/x/DxVG #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA #RepetitionOperators
Timing Windows w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #06
Переглядів 2,3 тис.Рік тому
This video is all about the introduction to Timing Windows with respect to SVA (System Verilog Assertions). EDA Playground Link:- www.edaplayground.com/x/Fsyc #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA #svatimingwindows
Implication Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #05
Переглядів 2,9 тис.Рік тому
This video is all about the introduction to Implication Operators with respect to SVA (System Verilog Assertions). EDA Playground Link:- www.edaplayground.com/x/YsEf #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA
Building blocks of SVA (System Verilog Assertions) SVA VIDEO #04
Переглядів 3,5 тис.Рік тому
This video is all about the introduction to Building blocks with respect to SVA (System Verilog Assertions). #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA
Built-in System Function in SVA (System Verilog Assertions) SVA VIDEO #03
Переглядів 6 тис.Рік тому
This video is all about the introduction to Built-in System Functions with respect to SVA (System Verilog Assertions). EDA Playground Link For $rose system function: www.edaplayground.com/x/LfTL #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA
Concept of call-backs w.r.p.t sv-uvm (System Verilog Version of UVM) Part-2 (Modified)
Переглядів 1,4 тис.Рік тому
This video is all about the concept of call-backs w.r.p.t System Verilog Version of UVM (Universal Verification Methodology) with a very simple example. Combinational adder verification using sv-uvm:- ua-cam.com/video/blAiR11Xv8k/v-deo.html EDA Playground Link:- edaplayground.com/x/wPQn #semiconductor #vlsi #uvm #uvm4verfication #svuvm #callbacks #vlsifaq #froentenddesignandverification #electr...
Concept of memory declaration in RAL w.r.p.t System Verilog Version of UVM -- SV-UVM RAL VIDEO #17
Переглядів 1,6 тис.Рік тому
This video is all about the concept of memory class declaration w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define mem class , how to define predictor & scoreboard classes in the environment , how to connect monitor analysis port with analysis implementation ports of predictor & scoreboard, for the DUT which has a single m...
Example of functional coverage for register w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #16
Переглядів 2,3 тис.Рік тому
This video is all about the concept of functional coverage for register with example w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define coverage for register, how to define predictor in the environment class, how to connect monitor and predictor, for the DUT which has a single register in it, with single field F0. EDA Play...
Example for explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #15
Переглядів 1,5 тис.Рік тому
This video is all about the concept of explicit prediction example w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define predictor in the environment class, how to connect monitor and predictor for the DUT which has a single register in it, with single field F0. EDA Playground link:- edaplayground.com/x/WTn8 Explicit predicti...
Explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #14
Переглядів 1,3 тис.Рік тому
This video is all about the concept of explicit prediction w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define predictor in the environment class, how to connect monitor and predictor for the DUT which has a single register in it, with single field F0. #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #se...
reset method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #13
Переглядів 1 тис.Рік тому
This video is all about the concept of reset method w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer). EDA Playground Link:- edaplayground.com/x/Unw7 #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #semiconductor #ral #uvm4verification #register_abstraction_layer #registersequence #uvmral #RAL
randomize method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #12
Переглядів 991Рік тому
This video is all about the concept of randomize method w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer). EDA Playground Link:- edaplayground.com/x/8na7 #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #semiconductor #ral #uvm4verification #register_abstraction_layer #registersequence #uvmral #RAL
Update method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #11
Переглядів 1,1 тис.Рік тому
This video is all about the concept of update method w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer). EDA Playground Link:- edaplayground.com/x/GBwe #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #semiconductor #ral #uvm4verification #register_abstraction_layer #registersequence #uvmral #RAL
Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #10
Переглядів 1,8 тис.Рік тому
Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #10
Predict method in SV-UVM RAL (Register Abstraction Layer) SV-UVM RAL VIDEO #09
Переглядів 2,4 тис.Рік тому
Predict method in SV-UVM RAL (Register Abstraction Layer) SV-UVM RAL VIDEO #09
front door write, read methods & backdoor poke, peek methods SV-UVM RAL VIDEO #08
Переглядів 3,7 тис.Рік тому
front door write, read methods & backdoor poke, peek methods SV-UVM RAL VIDEO #08
set, get, get_mirrored_value, and write methods in RAL SV-UVM RAL VIDEO #07
Переглядів 3,2 тис.Рік тому
set, get, get_mirrored_value, and write methods in RAL SV-UVM RAL VIDEO #07
Transaction, Agent, and Register sequence classes - SV-UVM RAL VIDEO #06
Переглядів 2,9 тис.Рік тому
Transaction, Agent, and Register sequence classes - SV-UVM RAL VIDEO #06
Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #05
Переглядів 4,4 тис.Рік тому
Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #05
Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #04
Переглядів 13 тис.Рік тому
Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #04
Array sorting methods w.r.p.t System Verilog
Переглядів 903Рік тому
Array sorting methods w.r.p.t System Verilog
Can we implement a NOT gate using AND gate?
Переглядів 356Рік тому
Can we implement a NOT gate using AND gate?
Objection mechanism w.r.p.t System Verilog version of UVM
Переглядів 2,3 тис.Рік тому
Objection mechanism w.r.p.t System Verilog version of UVM
Design & verification of Protocols using sv-hdl & sv-uvm
Переглядів 1,1 тис.Рік тому
Design & verification of Protocols using sv-hdl & sv-uvm
uvm_subscriber w.r.p.t sv-uvm "FC VIDEO #12"
Переглядів 2,2 тис.Рік тому
uvm_subscriber w.r.p.t sv-uvm "FC VIDEO #12"
Full adder coverage model using System Verilog (Linear TB) "FC VIDEO #11"
Переглядів 2 тис.Рік тому
Full adder coverage model using System Verilog (Linear TB) "FC VIDEO #11"
Very helpfull
Your the best thank you
How this activecount is displayed in waveform
@@MyINDIANway-yx1om in view tab, you will see assertion add this to waveform..
Can you send me your linkedin I'd.. I want to ask you some questions
@@MunsifMAhmad do you know why active count font increase
pls explain about pack/unpack, record and other methods also
How to get assertions report
saying that something is very simple every 20 seconds and just reading what's beign shown is not explaining and it does NOT make things any simpler
Your Explanations are very clear😇💥.It's easy to grasp the concepts quickly .
Thank you for SVA series 🤩really helpful
both bins functionallity is same the main difference is that generating or showing error msg in the simulator.if we donot want to see where errors occured we use ignore otherwise we use illegeal bins
I have used virtual sequence and I have given the warning "No default phase sequence for phase 'run'" as running. How is this case? I have no idea whether it can cause any deep issues for my program or not. Many thanks.
Great expectation for virtual sequence and sequencer
Please don't stop teaching vlsi concept specially sv and uvm
this is wonderful, finally i can understand functional coverage
Amazing Explanation. If possible can you please share the presentation.
HI, Can you share the EDA Link for the example you are showing above?? Also, thank you for such a detailed explanation of RAL.
@@trashbin-u1h Link is alredy there in the description ..
@@MunsifMAhmad Got it, Thank You
I am also looking for uvm_reg_callback tutorials. Please suggest.
Appreciate your efforts.
Appreciate your efforts.
Which class does the functional coverage class extend if I write this in UVM testbench? (maybe uvm_subscriber?) Many thanks.
Uvm?
Next level explanation... Thank you so much...The explanation is exactly what I was looking for (industry specific)👏🙌😊
When i click view there is no schematic option for me The options i got are less than your options
1613 Sasha Keys
Amazing ...Thanks for an excellent explaination.
pls suggest what to do when we have multiple monitors and one subscriber class
can you post the code and all that will maek us to explore the code on our own and get some good experience
Hi .. Already EDA playground link is there in the description section, pls have a look..
I watched all videos in single go ...it is Very informative and gives easy understanding of RAL....like others I am also waiting for next videos ...Thanks for RAL videos ...
we just driven wr_enb as 1 when write...and then how wr_enb got 0 and output came onto dout i did not understood ....
easy to understand and need more videos on UVM , THANK YOU AHMAD
jab b mai kuch badhiya content pata hun yt pr, kuch na kuch issue rehti hi hai, munsif bhai.....mic to recheck kr lete bhai...bahut sahi content hai, par clear sunai de tabto
Thanks u for explaining briefly
Indeep explanation with comments good job sir ji
very useful and easily explained . Than you Ahmed sir, one doubt ---Is phases are written for every component ??
Thank you so much, very clear and informative video
Glad it was helpful!
Please do something about audio quality.
Thank you very much for a wonderful series 🙏
Thank you so much. It helped me a lot
simple and best explanation , I have seen all of ur sv videos---------->simply superb .
Thank you so much 🙂
Good explanation... Thank you so much for this SVA lecture series...
So nice of you..
Hi! nice video. A question i have a UVM project, and one test called Testcase05 that never finish. How i can use +UVM_OBJECTION_TRACE in vsim directive if it no finish? Because the TRACE OBJECTION is in transcript when it finish...
we can also use (~a) || (b) instead of a |-> b ?
sir, I written verilog code for xor gate, cocotb testbench in python, wrappers and makefile. I got the output as TEST FAILED. but i can able to find the output value in console. Where to see the output value. i think there is an error in wrappers. How to fix it
can u plz expline the diffrence between non consicutive and go to
hi, could you explain me the meaning of yellow triangle, please? Many thanks.
Good explanation Sir. Try to create verification ip for Axi,Amba,JTAG, mmc protocols using cocotb for RTL/python Verification
in which component we write the code for coverage and Assertions ?????? and it is Design or Testbench ???
For coverage we can use uvm subscriber class..
Please upload further videos
Sure.. :)
what content you use to explain method's literature ?
Mostly UVM cookbook
Sir how to generate coverage coverage report using synopsys vcs
Will check and let u know..
Hi, I executed the same code, but i am getting error like unable to locate hdl path(DUT>tempreg0) and unable to locate hdl path (DUT.tempreg0)
run.do file is not working for my TB