Boolean expression implementation using Clocked CMOS logic

[@asifrahman461]

Pmos are parallel when they are doing AND operation right? but why you showing inverse things

[@InderjitSingh87]

In the pull-up network, PMOS are in parallel for AND operation. Can you explain, how they are inverse in the Clocked CMOS design covered.

[@InderjitSingh87]

Hope your doubt it cleared ?