Hi Matt, An amazing work! I believe you have made a mistake at 3:20. We can not fine total power (RF+DC) using 0.5*Vp*Ip. We can use this formula just when the time domain signal is a single tone without any DC component and any other tones. Thanks a lot!
Hi, thanks for the video. I have a question regarding the load line plot at 11:20 . Assuming the the plots in Id-Vds graph are for equally swept Vgs voltages, the Vgs swing has to be different in positive and negative directions to reach at the Imax and Vmax points. I have observed the same condition also when I simulate some real CMOS transistors. Am I missing something? Thanks in advance.
+Denizhan Karaca Good question! You are correct -- the transconductance of a CMOS device is not linear -it’s a square law relationship (Id is proportional to Vgs-Vt squared) . This means that the positive portion of the gate (or input) waveform experiences a higher effective gm than the negative portion of the waveform. You may find this video on the basic classes of operation [ua-cam.com/video/GhPqPVlDRPY/v-deo.html] interesting, as the nonlinearly which you refer to at the input is more explicitly illustrated (around 3:00). The video also shows that to get the classical values of efficiency for a power amplifier, the trans-conductance is linearized (Id is made proportional to Vgs-Vt) - or at least this is done in a mathematical sense to derive the waveforms and the corresponding ideal efficiency. Since no device actually behaves so nicely as to have a perfectly linear transconductance, you can therefore never realize the ideal efficiency values for a Power Amplifier in real life! This non-ideal transconductance also implies that there is no single bias point where the device will be exactly at the brink of turning on and off (the so called “threshold” in Class B where exactly half of the waveform perfectly conducts). Consequently, most amplifiers biased near the Class B threshold point have low or no small signal gain in the lab - in other words the Gain vs. Pout plot is highly expansive as power increases. One of the big challenges in any practical PA design is dealing with the effects of these types of non-idealities - in many cases what you can actually realize in the lab is far removed from the waveforms and loadlines that the theory implies. Depending on how you look at it, this can either be very disappointing or very exciting and interesting!
Thanks for the Nice Video. Have one Question @ 8.05, How can the current can be pulled from the ground?. I guess the extra current is coming from the Choke.
I have one question. You mentioned that "since less current is pulled into the current source, instead it flows in AC sense from the power supply into the load." There is a bias inductor after the supply and if we think of RF( or AC sense) this provides high impedance. So, how is the AC (or RF) current flowing from the supply through the inductor to the load ? Doesn't the inductor resist ac current flowing from the supply into the load ? Can you please explain a bit?
I would like to add another question: With the similar concept how to explain the envelope current( for modulated signals) flow from the supply to the device and the load for both class A and reduced conduction angle mode operation( class AB/B). Thanks.
These are questions that could take a book’s worth to answer. Briefly, the DC supply provides the energy to the circuit. At the fundamental, the transistor converts this DC energy to a high frequency. It then gets exchanged between the transistor and the RF load network without much further supply interaction (assuming the choke’s designed well). The combination of the current in the load and device will sum to the DC value over a cycle. For that to work (assuming no storage), the load current must go high when the device current goes low - this is kind of a redirection of current from transistor to load during the RF cycle. When there is a modulated signal, it contains the high frequency signal, but now there is a lower frequency envelope, changing the input power dynamically. Plot current vs. Pin to see how that may impact the dynamic draw from the supply. For Class A, if it never goes into compression, the DC current does not change much vs. Pin, as you move to Class AB, current does change more with Pin. That means the device will dynamically try to pull current from the supply at the mod bandwidth - and if the bias network is designed well, then the supply will be able to deliver the current dynamically when needed.
This is so amazing, one of the best videos I have ever watched in my life. Would you also please explain why the load has real and imaginary part. Since we always calculate and simulate for RL and load-line theory is based on that. But we always have imaginary part in load-pull simulation. Thank you for your time, I appreciate.
Great! Glad you found it useful! Device parasitics are the culprit. These reactive elements occur between the “ideal” current generator inside the device and the actual output terminal (ie the physical drain connection on your IC/package). The goal is to present a reactive impedance externally which is transformed by the parasitic elements so that it is a real load value intrinsically. In this example, the parasitic elements in the model were zeroed out, hence the real load value.
great series of videos. explanations are very well done....if possible and in future, a complete RF-Transmitter design explanation video (using ADS) will be interesting... thanks
Hey Matt, that was an awesome tutorial. However, I'd like to have your opinion on the impact of S22 on the performance of an RF Power Amplifier. And how it might effect the various Figures of Merit. Thanks. :)
THE LINK TO THE DISPLAY TEMPLATES IS NOT WORKING
Hi Matt,
An amazing work!
I believe you have made a mistake at 3:20. We can not fine total power (RF+DC) using 0.5*Vp*Ip. We can use this formula just when the time domain signal is a single tone without any DC component and any other tones.
Thanks a lot!
Yet another very good initiative by Keysight. Thanks for wonderful videos.
Great video! This is the most intuitive explanation of class A power amplifier. More useful than any textbook!
To The Gentleman @
Keysight EEsof EDA
A Big Thank You For Posting This Series On UA-cam!
Hi, thanks for the video. I have a question regarding the load line plot at 11:20 . Assuming the the plots in Id-Vds graph are for equally swept Vgs voltages, the Vgs swing has to be different in positive and negative directions to reach at the Imax and Vmax points. I have observed the same condition also when I simulate some real CMOS transistors. Am I missing something? Thanks in advance.
+Denizhan Karaca
Good question! You are correct -- the transconductance
of a CMOS device is not linear -it’s a square law relationship (Id is
proportional to Vgs-Vt squared) .
This means that the positive portion of
the gate (or input) waveform experiences a higher effective gm than the
negative portion of the waveform. You may find this video on the basic
classes of operation [ua-cam.com/video/GhPqPVlDRPY/v-deo.html] interesting, as the
nonlinearly which you refer to at the input is more explicitly illustrated
(around 3:00). The video also shows that to get the classical values of
efficiency for a power amplifier, the trans-conductance is linearized (Id is
made proportional to Vgs-Vt) - or at least this is done in a mathematical sense
to derive the waveforms and the corresponding ideal efficiency. Since no
device actually behaves so nicely as to have a perfectly linear
transconductance, you can therefore never realize the ideal efficiency values
for a Power Amplifier in real life!
This non-ideal transconductance also implies that there is
no single bias point where the device will be exactly at the brink of turning
on and off (the so called “threshold” in Class B where exactly half of the
waveform perfectly conducts). Consequently, most amplifiers biased near
the Class B threshold point have low or no small signal gain in the lab - in
other words the Gain vs. Pout plot is highly expansive as power
increases.
One of the big challenges in any practical PA design is
dealing with the effects of these types of non-idealities - in many cases what
you can actually realize in the lab is far removed from the waveforms and
loadlines that the theory implies.
Depending on how you look at it, this
can either be very disappointing or very exciting and interesting!
+Keysight EEsof EDA Thanks for your detailed explanation, it is very clear and helpful.
Keysight EEsof ED
Thanks for the Nice Video. Have one Question @ 8.05, How can the current can be pulled from the ground?. I guess the extra current is coming from the Choke.
What is the value of Vp and Ip?
Thanks for your elucidation about the basics of PA
The project file link is not working. Please upload the updated link
Hi, Can you show me how can we get these plots?
ME TOO
请问这里的Vp和Ip是多少啊，怎么计算峰值
Hi pliz i found prb in the installation of ads, in lecence server
I have one question. You mentioned that "since less current is pulled into the current source, instead it flows in AC sense from the power supply into the load." There is a bias inductor after the supply and if we think of RF( or AC sense) this provides high impedance. So, how is the AC (or RF) current flowing from the supply through the inductor to the load ? Doesn't the inductor resist ac current flowing from the supply into the load ? Can you please explain a bit?
I would like to add another question: With the similar concept how to explain the envelope current( for modulated signals) flow from the supply to the device and the load for both class A and reduced conduction angle mode operation( class AB/B). Thanks.
These are questions that could take a book’s worth to answer. Briefly, the DC supply provides the energy to the circuit. At the fundamental, the transistor converts this DC energy to a high frequency. It then gets exchanged between the transistor and the RF load network without much further supply interaction (assuming the choke’s designed well). The combination of the current in the load and device will sum to the DC value over a cycle. For that to work (assuming no storage), the load current must go high when the device current goes low - this is kind of a redirection of current from transistor to load during the RF cycle.
When there is a modulated signal, it contains the high frequency signal, but now there is a lower frequency envelope, changing the input power dynamically. Plot current vs. Pin to see how that may impact the dynamic draw from the supply. For Class A, if it never goes into compression, the DC current does not change much vs. Pin, as you move to Class AB, current does change more with Pin. That means the device will dynamically try to pull current from the supply at the mod bandwidth - and if the bias network is designed well, then the supply will be able to deliver the current dynamically when needed.
@@KeysightEEsofEDA Many thanks for the detailed answer. I really appreciate that.
Great video. I appreciate the concise refresher as a working professional trying not to bug my FAEs every week :)
The link in the description appears to be dead for this series. Where can I find?
Where are V_t and I_t defined in data display. I cant find them as eqn in simple_power display page
Hello, I need to know how to do loadpull simulation for a Push Pull RF Power Transistor (with 5 pins). Thanks in advance.
Can you please tell me what the phrase “up mixing “ means pls
Many thanks to you. This is helpful and easy to follow! Cheers.
This is so amazing, one of the best videos I have ever watched in my life.
Would you also please explain why the load has real and imaginary part. Since we always calculate and simulate for RL and load-line theory is based on that. But we always have imaginary part in load-pull simulation.
Thank you for your time, I appreciate.
Great! Glad you found it useful! Device parasitics are the culprit. These reactive elements occur between the “ideal” current generator inside the device and the actual output terminal (ie the physical drain connection on your IC/package). The goal is to present a reactive impedance externally which is transformed by the parasitic elements so that it is a real load value intrinsically. In this example, the parasitic elements in the model were zeroed out, hence the real load value.
great series of videos. explanations are very well done....if possible and in future, a complete RF-Transmitter design explanation video (using ADS) will be interesting...
thanks
+zianadir Thanks! And we love your suggestion...stay tuned!
+Keysight EEsof EDA any update?
thank you for your efforts
brilliant explanation
i am a student in UESTC, thank you for your video wih Chinese captions
One word: Brilliant!
Hey Matt, that was an awesome tutorial. However, I'd like to have your opinion on the impact of S22 on the performance of an RF Power Amplifier. And how it might effect the various Figures of Merit. Thanks. :)
+Sheikh Aamir Ahsan Great question! Matt answered! Check out the blog article: rfdesigntips.blogs.keysight.com/
@@KeysightEEsofEDA can you please reshare the link?
Who here is watching this cuz u got a research paper to write?
Thank you, nice tutorials.
excelente tutorial gracias
great explanation!!! video should have much more views .. thanks man
这视频可太牛逼了，国内少有这种讲解性的精品视频。
Cheers to keysight =)
So good. Thank you.
Directions not clear FBI at door
Good and informative but goes way too fast
hindi mein vidio banaye