Intel Quartus: Connecting Modules in Verilog

Поділитися
Вставка
  • Опубліковано 11 січ 2025

КОМЕНТАРІ • 12

  • @johnrex5342
    @johnrex5342 2 роки тому +6

    This is the best explanation I've seen on UA-cam.

  • @fakehesap9365
    @fakehesap9365 4 роки тому

    thanks Jay you are the best

  • @emigdioalaniz
    @emigdioalaniz Рік тому

    you have more files on how to do modules or any book to use ??/

  • @M4DA.
    @M4DA. 6 років тому

    Thans Jay, very helpful ;)

  • @3liam7md123
    @3liam7md123 3 роки тому

    you're the best!!

  • @kevinsarmiento4275
    @kevinsarmiento4275 2 роки тому

    youre my goat

  • @TooSlowTube
    @TooSlowTube 2 роки тому

    Do names in a module inside another module always have to start with a dot?
    Is that the only situation where a name starts with a dot?

    • @gabrielladangler1722
      @gabrielladangler1722 Рік тому +1

      From how I understand it, if you are using explicit declarations, then yes. I believe it means that the value should be referenced from the original module from which the instantiation is made. For example, the ".a" above pulls in the declaration of "a" from the module "myAND" and assigns it to the input declared in the current module, "input a". I hope this makes sense!

    • @TooSlowTube
      @TooSlowTube Рік тому

      @@gabrielladangler1722 Thanks.

  • @CuongNguyen-id1ob
    @CuongNguyen-id1ob 4 роки тому

    Thanks so much for this useful tutorial!

  • @fakehesap9365
    @fakehesap9365 4 роки тому

    sen var ya adamsın

  • @thebullybuffalo
    @thebullybuffalo 4 роки тому +9

    Bruh why would you make the ports the same name? So unecessarily confusing