Using Multiple Modules in Verilog

[@anastasiakarpelevich25]

this is fire
you rock
I'm impressed that you did almost everithing in vs code

[@tuanazzam6320]

for sure it is a most useful lesson I watched in youtube.. keep it up...

[@amarjeetsaini9320]

do we have to include all the submodule into the main module.v (or) is the any other way similar to programming language class using header file (because for complex circuit main module file would become large) ?

[@abbyamonett9255]

This video is super helpful and well done, thank you!

[@gatau_pusing]

is there a specific reason why do we write the output with the combination of AND gate like that for every index of D? can I write it differently?

[@carriersignal]

Great video! Very Helpful. Thank you.

[@prithivimaruthachalam8647]

I get a "macro include undefined" when I try to include files and I was not able to find anything information on that.

[@nanayang3736]

What does the #20 behind each assignment of values mean? I feel that I might have accidentally skipped that part.

[@rajdeep5126]

its just timeperiod of 20 ns for each transition from 0 to 1 and vice-versa

[@ravirajac]

I want to learn Verilog and also want to practice. Can you please suggest the steps to take? I want to be very good at it. Iknow digital electronics already. thank

[@alwatt8011]

CRystal-clear!

[@ingframin]

Can you put the code on github?

[@mohamedgharbi7582]

thanks very helpful