[@ArifMahmood]

SV and RTL code:
github.com/aarifboy/verilogvsvhdl/blob/main/and_gate.sv
SV RTL testbench:
github.com/aarifboy/verilogvsvhdl/blob/main/test_and.sv
VHDL and RTL code:
github.com/aarifboy/verilogvsvhdl/blob/main/and_gate.vhd
VHDL RTL testbench:
github.com/aarifboy/verilogvsvhdl/blob/main/test_and.vhd