1) define width and height of core and die 2) define location of preplaced cells(macros or IP) 3) surround preplaced cells with Decoupling Capacitors 4) Power Planning 5)Pin Placement 6) Logical cell placement blockage
Hey There, Great news...STA-2 course is now 90% completed and I am all geared up to pre-launch my next course on "CCS Libraries - Syntax and Constructs" (title is subject to change), which is the "Heart of Physical Design and Static Timing Analysis". A PNR or STA engineer without the knowledge of Libraries is like a body without the soul. Now, if you really want to be successful in this domain, knowledge of body and soul should be deep embodied into your heart and mind. Let's start with the body first. To be eligible to enroll in my next course on CCS libraries, knowledge of physical design and STA should be 100% (my courses are enough to get started with, you can also look for alternatives). The reviews have been awesome for my courses. Here’s one of them:“The fundamentals are explored in deep and explanations are very precise. This course is very helpful for the beginners.” Here’s another one:“The instructor is very adapt at explaining concepts using analogies that everyone can understand and relate to, which is really great. It is rare to find an instructor that is both intelligent and able to drive home theories and concepts so clearly and in a way that is easy to understand. I will buy all the classes from him. Keep up the good work.” Based on feedback from you, I am releasing one last coupon for $10 that will expire tomorrow mid-night i.e. on 5th Jan' 2017 11:59pm IST. Below are the links for the same: Static Timing Analysis - Part 1: www.udemy.com/vlsi-academy-sta-checks/?couponCode=JAN_10DOLLAR Static Timing Analysis - Part 2: www.udemy.com/vlsi-academy-sta-checks-2/?couponCode=JAN_10DOLLAR Physical design flow:www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=JAN_10DOLLAR Make sure you enroll right now and take the fullest advantage of completing them 100% before my release of next course on CCS Libraries On the same eve, I am glad to announce more than 90% discount on all of my other courses as well, and every course being 100% completed is an add-on to “CCS Library course” understanding. Below are the links for them as well, and they too expire tomorrow mid-night i.e. on 5th Jan' 2017 11:59pm IST Custom Layout: www.udemy.com/vlsi-academy-custom-layout/?couponCode=JAN_10DOLLAR Clock tree synthesis - Part 2:www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=JAN_10DOLLAR Circuit design and SPICE simulations - Part 2:www.udemy.com/vlsi-academy-circuit-design-part2/?couponCode=JAN_10DOLLAR Circuit design and SPICE simulations - Part 1:www.udemy.com/vlsi-academy-circuit-design/?couponCode=JAN_10DOLLAR Signal integrity: www.udemy.com/vlsi-academy-crosstalk/?couponCode=JAN_10DOLLAR Clock tree synthesis - Part 1:www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=JAN_10DOLLAR VLSI - Essential concepts and detailed interview guide:www.udemy.com/vlsi-academy/?couponCode=JAN_10DOLLAR “The ladder of success is best-climbed by stepping on the rungs of opportunity” - Ayn Rand Climb it now….till then … happy learning….
+syed tahauddin I'm no expert but Proteus and Eagle are used for PCB layout and assembling the layout of relatively large components. When you're on nano-meter scale involving millions of transistors, you have to go for tools from Cadence, Synopsys, Mentor. and yes they are pretty pretty costly.
Hello Varun, Many vendors (Cadence/Synopsys/Mentor), have their own tools like cadence Encounter, Synposys ICC, etc. do the above required jobs Thanks VSD Team
1) define width and height of core and die
2) define location of preplaced cells(macros or IP)
3) surround preplaced cells with Decoupling Capacitors
4) Power Planning
5)Pin Placement
6) Logical cell placement blockage
Hey There,
Great news...STA-2 course is now 90% completed and I am all geared up to pre-launch my next course on "CCS Libraries - Syntax and Constructs" (title is subject to change), which is the "Heart of Physical Design and Static Timing Analysis". A PNR or STA engineer without the knowledge of Libraries is like a body without the soul.
Now, if you really want to be successful in this domain, knowledge of
body and soul should be deep embodied into your heart and mind. Let's
start with the body first. To be eligible to enroll in my next course on
CCS libraries, knowledge of physical design and STA should be 100% (my
courses are enough to get started with, you can also look for
alternatives).
The reviews have been awesome for my courses. Here’s one of them:“The fundamentals are explored in deep and explanations are very precise. This course is very helpful for the beginners.”
Here’s another one:“The instructor is very adapt at explaining concepts using analogies that everyone can understand and relate to, which is really great. It is rare to find an instructor that is both intelligent and able to drive home theories and concepts so clearly and in a way that is easy to understand. I will buy all the classes from him. Keep up the good work.”
Based on feedback from you, I am releasing one last coupon for $10 that will expire tomorrow mid-night i.e. on 5th Jan' 2017 11:59pm IST. Below are the links for the same:
Static Timing Analysis - Part 1:
www.udemy.com/vlsi-academy-sta-checks/?couponCode=JAN_10DOLLAR
Static Timing Analysis - Part 2:
www.udemy.com/vlsi-academy-sta-checks-2/?couponCode=JAN_10DOLLAR
Physical design flow:www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=JAN_10DOLLAR
Make sure you enroll right now and take the fullest advantage of completing them 100% before my release of next course on CCS Libraries
On the same eve, I am glad to announce more than 90% discount on all of my other courses as well, and every course being 100% completed is an add-on to “CCS
Library course” understanding. Below are the links for them as well, and they too expire tomorrow mid-night i.e. on 5th Jan' 2017 11:59pm IST
Custom Layout: www.udemy.com/vlsi-academy-custom-layout/?couponCode=JAN_10DOLLAR
Clock tree synthesis - Part 2:www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=JAN_10DOLLAR
Circuit design and SPICE simulations - Part 2:www.udemy.com/vlsi-academy-circuit-design-part2/?couponCode=JAN_10DOLLAR
Circuit design and SPICE simulations - Part 1:www.udemy.com/vlsi-academy-circuit-design/?couponCode=JAN_10DOLLAR
Signal integrity:
www.udemy.com/vlsi-academy-crosstalk/?couponCode=JAN_10DOLLAR
Clock tree synthesis - Part 1:www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=JAN_10DOLLAR
VLSI - Essential concepts and detailed interview guide:www.udemy.com/vlsi-academy/?couponCode=JAN_10DOLLAR
“The ladder of success is best-climbed by stepping on the rungs of opportunity” - Ayn Rand
Climb it now….till then … happy learning….
Thanks a lot
Useful stuff. Thank you:) . Thanks for social service :)
Which software are you using here.?????
Hi,
When do we place standard cell ? is it missing ? :S
How to get fre tool acess
useful
Please share designing core and die area link
Macros wont contain logic na..those are just for memory..am i correct?
logic also contain but macro are design by other team
Not all macros are memories, but memories are macros
cant this be simulated on Proteus software or Eagle software...?
Is ICC from Synopsys an open source software.?
syed tahauddin No, synopsys costs a great deal of money
+syed tahauddin I'm no expert but Proteus and Eagle are used for PCB layout and assembling the layout of relatively large components.
When you're on nano-meter scale involving millions of transistors, you have to go for tools from Cadence, Synopsys, Mentor.
and yes they are pretty pretty costly.
what are the tools?
Hello Varun,
Many vendors (Cadence/Synopsys/Mentor), have their own tools like cadence Encounter, Synposys ICC, etc. do the above required jobs
Thanks
VSD Team
can you make video about cadence tools tutorials??
what are the tools used to do placement and routing in the chip??
Hello Dipan Kar,
Cadence Encounter, Synposys ICC are generally used for Placement and Routing
Thanks
VSD Team